Datasheet > ZL40295

ZL40295

更新时间： 2024-11-30 14:55:23

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
38页	1457K
描述
The ZL40295 is part of a family of high-performance, ultra-low jitter, low power 1 to 20 HCSL fano

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ZL40295 数据手册

Data Sheet

ZL40295

20-Output PCIe Gen 1, 2, 3, 4 and 5 Buffer with Ultra-Low

Additive Jitter

Ordering Information

Features

ZL40295LDG6

ZL40295LDF6

80 pin GQFN Trays

80 pin GQFN Tape and Reel

• Fully Compliant with PCIe Gen 1, 2, 3 , 4, and 5.

• 20 Low-Power Push-Pull HCSL PCIe Outputs

• Ultra-low additive jitter: 10fs for PCIe 5.0

• Supports clock frequencies from 0 to 250MHz

• Supports 3.3V power supplies

Package size: 6 x 6 mm



-40 C to +85 C

Applications

• Embedded Low Drop Out (LDO) Voltage regulator

•

PCI Express generation 1/2/3/4/5 clock distribution

provides superior Power Supply Noise Rejection

Intel QPI

• Maximum output to output skew of 50ps

• SMBus Interface

Servers

Storage and Data Centers

Switches and Routers

• Side-Band Interface (SBI)

• Eight OE pins

• Embedded series termination resistors for 100Ω

differential transmission line

• Transparent for Spread Spectrum Clock

VDD

VDD_A

CK_IN

CK[19:0]

CK_IN#

^vSA0_tri

^vSA1_tri

SMBDAT

Control

Logic

SMBCLK

PWRGD/PWRDN#

vOE#[12:5]/SBI

RFU

GND_A

GND

Prefix vꢀꢁimplies 120kꢂ pull-down resistor

Prefix ꢃvꢀꢁimplies 120kꢂꢁpull-up and 120kꢂꢁpull-down resistors (VDD/2 bias)

Figure 1. Functional Block Diagram

ZL40295

December 2019

12 3 4 5 6 7...38

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