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ZL40250 PDF预览

ZL40250

更新时间: 2024-11-07 14:52:27
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美国微芯 - MICROCHIP /
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描述
CREATE AND SAMPLE YOUR CUSTOM ZL40250 HERE The ZL40250 is a 6-output programmable fanout buffer w

ZL40250 数据手册

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Register Map: Section 5.2  
TM  
ZL40250ZL40253 SmartBuffer  
6- or 10-Output Programmable Fanout  
Buffers with Multi-Format I/O and Dividers  
Data Sheet  
September 2020  
Features  
Ordering Information  
Four Flexible Input Clocks  
One crystal/CMOS input  
Two differential/CMOS inputs  
One single-ended/CMOS input  
ZL40250LDG1  
ZL40250LDF1  
ZL40251LDG1  
ZL40251LDF1  
ZL40252LDG1  
ZL40252LDF1  
ZL40253LDG1  
ZL40253LDF1  
ext. EEPROM  
ext. EEPROM  
int. EEPROM  
int. EEPROM  
ext. EEPROM  
ext. EEPROM  
int. EEPROM  
int. EEPROM  
6 Outputs  
6 Outputs  
6 Outputs  
6 Outputs  
10 Outputs  
10 Outputs  
10 Outputs  
10 Outputs  
Trays  
Tape and Reel  
Trays  
Tape and Reel  
Trays  
Tape and Reel  
Trays  
Tape and Reel  
Any input frequency up to 1GHz (300MHz for  
Matte Tin  
Package size: 8 x 8 mm, 56 Pin QFN  
CMOS)  
-40 C to +85 C  
Manual clock switching by pin or register  
6 or 10 Universal Output Clocks with Dividers  
Each output has independent divider  
General Features  
Automatic self-configuration at power-up from  
external (ZL40250or 2) or internal (ZL40251or 3)  
EEPROM; up to 8 configurations pin-selectable  
Low additive jitter <200fs RMS (12kHz-20MHz,  
for input frequencies 100MHz)  
PCIe 1, 2, 3, 4 compliant  
Four multi-purpose I/O pins  
SPI or I2C processor Interface  
Each output configurable as LVDS, LVPECL,  
HCSL, 2xCMOS or HSTL  
In 2xCMOS mode, the P and N pins can be  
different frequencies (e.g. 125MHz and 25MHz)*  
Core supply voltage options: 2.5V only, 3.3V  
Multiple output supply voltage banks with  
only, 1.8V+2.5V or 1.8V+3.3V  
CMOS output voltages from 1.5V to 3.3V  
Space-saving 8x8mm QFN56 (0.5mm pitch)  
Easy-to-use evaluation/programming software  
Precise output alignment circuitry from GPIO  
pin or register bit*  
Applications  
Per-output skew adjustment*  
Clock signal fanout, format conversion, frequency  
division and skew adjustment in a wide variety of  
equipment types  
Per-output enable/disable and glitchless  
start/stop (stop high or low) *  
VDDOA  
OC1P, OC1N  
DIV1  
DIV2  
DIV3  
DIV4  
DIV5  
DIV6  
DIV7  
DIV8  
DIV9  
DIV  
DIV  
DIV  
IC1P, IC1N  
IC2P, IC2N  
IC3P  
Path 1  
Path 2  
OC2P, OC2N  
VDDOB  
OC3P, OC3N  
VDDOC  
XA  
XB  
xtal  
driver  
DIV  
OC4P, OC4N  
OC5P, OC5N  
VDDOD  
OC6P, OC6N  
10-output  
devices only  
RSTN  
AC0/GPIO0  
AC1/GPIO1  
AC2/GPIO2  
TEST/GPIO3  
IF0/CSN  
OC7P, OC7N  
VDDOE  
OC8P, OC8N  
VDDOF  
Microprocessor  
Port  
(SPI or I2C Serial)  
OC9P, OC9N  
and GPIO Pins  
IF1/MISO  
SCL/SCLK  
SDA/MOSI  
OC10P, OC10N  
DIV10  
Figure 1 - Functional Block Diagram  
* some features require a higher-frequency input clock and enabling the output dividers  
1
Microsemi Confidential  
Copyright 2020. Microsemi Corporation. All Rights Reserved.  
 

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