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ZL40262 PDF预览

ZL40262

更新时间: 2024-11-07 14:53:59
品牌 Logo 应用领域
美国微芯 - MICROCHIP PC
页数 文件大小 规格书
26页 916K
描述
The ZL40262 is part of a family of high-performance, ultra-low jitter and low power PCIe Gen 1 to

ZL40262 数据手册

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Data Sheet  
ZL40262  
Two output ultra-low additive phase noise PCIe Gen 1 to 5,  
and UPI/QPI fanout buffer  
Ordering Information  
Features  
ZL40262LDG1  
ZL40262LDF1  
20 pin QFN  
20 pin QFN  
Trays  
Tape and Reel  
One differential input which accepts any  
differential format.  
Package size: 4 x 4 mm  
Two differential HCSL outputs  
-40 C to +85 C  
Ultra-low additive jitter: 32fs (in 12kHz to 20MHz  
integration band at 400MHz clock frequency)  
Applications  
Supports clock frequencies from 0 to 400MHz  
PCI Express generation 1/2/3/4/5 clock distribution  
UPI/QPI clock distribution  
Supports 2.5V or 3.3V power supplies for HCSL  
outputs  
Low jitter clock trees  
Embedded Low Drop Out (LDO) Voltage regulator  
Logic translation  
provides superior Power Supply Noise Rejection  
Clock and data signal restoration  
High performance microprocessor clock distribution  
Test Equipment  
Maximum output to output skew of 50ps  
Individual Output Enable pin for each differential  
pair  
Transfers Spread-Spectrum without attenuation  
OE[1:0]_b  
OUT0_p  
OUT0_n  
IN_p  
IN_n  
OUT1_p  
OUT1_n  
ZL40262  
Figure 1. Functional Block Diagram  
ZL40262  
June 2019  
1
© 2019 Microsemi Corporation  
 
 
 

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