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ZL30772LFG7 PDF预览

ZL30772LFG7

更新时间: 2024-11-24 02:49:59
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
6页 362K
描述
IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers

ZL30772LFG7 数据手册

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ZL30771, ZL30772, ZL30773  
IEEE 1588 & Synchronous Ethernet  
Packet Clock Network Synchronizers  
Product Brief  
November 2019  
Features  
Ordering Information  
One, Two or Three DPLL Channels  
ZL30771LFG7 1-Channel 80-lead LGA Trays  
ZL30772LFG7 2-Channel 80-lead LGA Trays  
ZL30773LFG7 3-Channel 80-lead LGA Trays  
Packet and/or physical-layer frequency, phase  
and time synchronization  
Physical-layer compliance with ITU-T G.8262,  
G.8261.1, G.813, G.812, Telcordia GR-1244,  
GR-253  
NiAu (Pb-free)  
Package size: 11 x 11 mm  
-40 C to +85 C  
Packet-timing compliance with ITU-T G.8261,  
G.8263, G.8273.2 (class A, B, C, D), G.8273.4  
Per-output programmable duty cycle  
Enables 5G wireless applications with sub-  
Precise output alignment circuitry and per-  
100ns time/phase alignment requirements  
output phase adjustment  
Programmable bandwidth, 0.1mHz to 470Hz  
Hitless reference switching and mode switching  
High-resolution holdover averaging  
Per-output enable/disable and glitchless  
start/stop (stop high or low)  
Local Oscillator  
Programmable phase slope limit for transients,  
Operates from a single TCXO or OCXO: 23.75-  
downto 1 ns/s  
25MHz, 47.5-50MHz, 114.285-125MHz  
Per-DPLL phase adjustment, 1ps resolution  
Very-low-jitter applications can connect a TCXO  
or OCXO as the stability reference and a low-  
jitter XO as the jitter reference  
Input Clocks  
Accepts up to 10 differential or CMOS inputs  
Any input frequency from 0.5Hz to 900MHz  
Per-input activity and frequency monitoring  
Automatic or manual reference switching  
Fast lock to 1 PPS input, <30 seconds  
General Features  
Automatic self-configuration at power-up from  
internal Flash memory  
Input-to-output alignment <2ns  
Internal compensation (1ppt) for local oscillator  
Any input can be a 1PPS SYNC input for  
frequency error in DPLLs and input monitors  
REF+SYNC frequency/phase/time locking  
Numerically controlled oscillator behavior in  
Per-input phase adjustment, 1ps resolution  
Output Clock Frequency Generation  
each DPLL and each fractional output divider  
Programmable Time of Day counters  
Any output frequency from <0.5Hz to 1045MHz  
Easy-to-configure design requires no external  
(180MHz max for Synth0)  
VCXO or loop filter components  
High-resolution fractional frequency conversion  
7 GPIO pins with many possible behaviors  
SPI or I2C processor Interface  
with 0ppm error  
Synthesizers 1 & 2 have integer and fractional  
1.8V and 3.3V core VDD voltages  
dividers to make a total of 5 frequency families  
Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out  
Easy-to-use evaluation/programming software  
Factory programmable power-up configuration  
Output jitter from Synths 1 & 2 is <0.3ps RMS  
Output jitter from fractional dividers is typically  
< 1ps RMS, many frequencies <0.5ps RMS  
Each HPOUTP/N pair can be LVDS, LVPECL,  
Applications  
HCSL, 2xCMOS, HSTL or programable diff.  
Central system timing ICs for SyncE and/or  
IEEE 1588, SONET/SDH, OTN, wireless base  
station and other carrier-grade systems  
Four output banks each with VDDO pin; CMOS  
output voltages from 1.5V to 3.3V  
Per-synthesizer phase adjust, 1ps resolution  
G.8262/813 EEC/SEC, Telcordia Stratum 2-4  
1
Microsemi Confidential  
Copyright 2019. Microsemi Corporation. All Rights Reserved.  

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