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ZL38002DGE1 PDF预览

ZL38002DGE1

更新时间: 2024-11-23 03:08:35
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 数字传输接口电信集成电路电信电路光电二极管综合业务数字网
页数 文件大小 规格书
51页 579K
描述
Digital Echo Canceller for Hands Free Communication

ZL38002DGE1 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:SSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.64
Is Samacsys:NJESD-30 代码:S-PDSO-G36
JESD-609代码:e3长度:15.3 mm
湿度敏感等级:3功能数量:1
端子数量:36最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:SQUARE
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:2.64 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ISDN ECHO CANCELLER温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

ZL38002DGE1 数据手册

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ZL38002  
Digital Echo Canceller for Hands Free  
Communication  
Data Sheet  
January 2007  
Features  
Ordering Information  
112 ms acoustic echo canceller  
Up to 12 dB of noise reduction  
ZL38002QDG  
48 Pin TQFP  
Trays  
ZL38002QDG1 48 Pin TQFP* Trays  
ZL38002DGE1 36 Pin QSOP* Tubes, Bake & Drypack  
ZL38002DGF1 36 Pin QSOP* Tape & Reel,  
Bake & Drypack  
Works with low cost voice codec. ITU-T G.711 or  
signed mag µ/A-Law, or linear 2’s compliment  
Each port may operate independently in  
*Pb Free Matte Tin  
-40°C to 85°C  
companded format or linear format  
Advanced NLP design - full duplex speech with  
no switched loss on audio paths  
User gain control provided for speaker path  
(-24 dB to +21 dB in 3 dB steps)  
Adjustable gain pads from -24 dB to +21 dB at  
Xin, Sin and Sout to compensate for different  
system requirements  
Fast re-convergence time: tracks changing echo  
environment quickly  
Adaptation algorithm converges even during  
Double-Talk  
Designed for exceptional performance in high  
AGC on speaker path  
background noise environments  
Handles up to -6 dB acoustic echo return loss  
Provides protection against narrow-band signal  
divergence  
(with the appropriate gain pad settings)  
Transparent data transfer and mute options  
20 MHz master clock operation  
Low power mode during PCM Bypass  
Bootloadable for future factory software upgrades  
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs  
Howling prevention stops uncontrolled oscillation  
in high loop gain conditions  
Programmable offset nulling of all PCM channels  
Serial micro-controller interface  
Idle channel noise suppression  
ST-BUS, GCI, or variable-rate SSI PCM  
interfaces  
Limiter  
S1  
S2  
+
Noise  
Reduction  
µ/A-Law/  
Linear/  
ADV  
NLP  
Gain  
Pad  
HP  
Gain  
Pad  
+
Sin  
Sout  
Linear  
µ/A-Law  
Filter  
-
DATA1  
DATA2  
MD1  
Program  
RAM  
NBSD  
Micro  
Interface  
CONTROL  
UNIT  
Program  
ROM  
Adaptive  
Filter  
Double  
Talk  
Gain  
Pad  
Detector  
Howling  
Controller  
NBSD  
R1  
1  
SCLK  
CS  
MD2  
Rout  
-24 -> +21dB  
HP  
User  
Gain  
µ/A-Law/  
Linear/  
µ/A-Law  
Rin  
AGC  
Filter  
Linear  
Limiter  
VSS  
VDD  
BCLK/C4i  
FORMAT  
ENA1  
MCLK  
RESET  
ENA2  
LAW  
F0i  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved.  

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