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ZL38002DGB1 PDF预览

ZL38002DGB1

更新时间： 2024-11-18 22:29:35
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 数字传输接口电信集成电路电信电路光电二极管综合业务数字网
页数 文件大小 规格书
47页 441K
描述
Low-Voltage Acoustic Echo Canceller With Noise Reduction

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ZL38002DGB1 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：SSOP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.64
Is Samacsys：NJESD-30 代码：R-PDSO-G36
JESD-609代码：e3长度：15.3 mm
功能数量：1端子数量：36
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.64 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ISDN ECHO CANCELLER
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：7.5 mmBase Number Matches：1

ZL38002DGB1 数据手册

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ZL38002  
Low-Voltage Acoustic Echo Canceller  
with Noise Reduction  
Data Sheet  
August 2005  
Features  
Ordering Information  
•
•
•
112 ms acoustic echo canceller  
Up to 12 dB of noise reduction  
ZL38002QDG  
48 Pin TQFP Trays  
ZL38002QDG1 48 Pin TQFP* Trays  
ZL38002DGA1 36 Pin QSOP* Tubes  
ZL38002DGB1 36 Pin QSOP* Tape and Reel  
Works with low cost voice codec. ITU-T G.711 or  
signed mag µ/A-Law, or linear 2’s compliment  
•
•
•
•
•
•
•
Each port may operate independently in  
companded format or linear format  
* Pb Free Matte Tin  
Advanced NLP design - full duplex speech with  
no switched loss on audio paths  
-40°C to 85°C  
Fast re-convergence time: tracks changing echo  
environment quickly  
•
•
User gain control provided for speaker path  
(-24 dB to +21 dB in 3 dB steps)  
Adaptation algorithm converges even during  
Double-Talk  
Adjustable gain pads from -24 dB to +21 dB at  
Xin, Sin and Sout to compensate for different  
system requirements  
Designed for exceptional performance in high  
background noise environments  
•
•
AGC on speaker path  
Provides protection against narrow-band signal  
divergence  
Handles up to -6 dB acoustic echo return loss  
(with the appropriate gain pad settings)  
Howling prevention stops uncontrolled oscillation  
in high loop gain conditions  
•
•
•
•
•
Transparent data transfer and mute options  
20 MHz master clock operation  
•
•
•
•
Programmable offset nulling of all PCM channels  
Serial micro-controller interface  
Low power mode during PCM Bypass  
Bootloadable for future factory software upgrades  
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs  
Idle channel noise suppression  
ST-BUS, GCI, or variable-rate SSI PCM  
interfaces  
Limiter  
S1  
S2  
+
Noise  
Reduction  
µ/A-Law/  
Linear  
Linear/  
µ/A-Law  
ADV  
NLP  
Gain  
Pad  
HP  
Filter  
Gain  
Pad  
+
Sin  
Sout  
-
DATA1  
DATA2  
MD1  
Program  
RAM  
NBSD  
Micro  
Interface  
CONTROL  
UNIT  
Program  
ROM  
Adaptive  
Filter  
Double  
Talk  
Detector  
Gain  
Pad  
Howling  
NBSD  
Controller  
R1  
1  
SCLK  
CS  
MD2  
Rout  
-24 -> +21dB  
HP  
Filter  
User  
Gain  
µ/A-Law/  
Linear  
Linear/  
µ/A-Law  
Rin  
AGC  
Limiter  
VSS  
VDD  
BCLK/C4i  
FORMAT  
ENA1  
MCLK  
RESET  
ENA2  
LAW  
F0i  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.  
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