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ZL38001QDC PDF预览

ZL38001QDC

更新时间: 2024-11-18 22:34:27
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 数字传输接口电信集成电路电信电路综合业务数字网
页数 文件大小 规格书
47页 646K
描述
Low-Voltage Acoustic Echo Canceller with Low ERL Compensation

ZL38001QDC 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:HTFQFP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.76
Is Samacsys:NJESD-30 代码:S-PQFP-G48
JESD-609代码:e0长度:7 mm
湿度敏感等级:3功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HTFQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.2 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ISDN ECHO CANCELLER温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
Base Number Matches:1

ZL38001QDC 数据手册

 浏览型号ZL38001QDC的Datasheet PDF文件第2页浏览型号ZL38001QDC的Datasheet PDF文件第3页浏览型号ZL38001QDC的Datasheet PDF文件第4页浏览型号ZL38001QDC的Datasheet PDF文件第5页浏览型号ZL38001QDC的Datasheet PDF文件第6页浏览型号ZL38001QDC的Datasheet PDF文件第7页 
ZL38001  
Low-Voltage Acoustic Echo Canceller  
with Low ERL Compensation  
Data Sheet  
June 2004  
Features  
Contains two echo cancellers: 112 ms acoustic  
echo canceller  
Ordering Information  
Works with low cost voice codec. ITU-T G.711 or  
signed mag µ/A-Law, or linear 2’s comp  
ZL38001DGA 36 Pin QSOP  
ZL38001QDC 48 Pin TQFP  
Each port may operate in different format  
-40°C to +85°C  
Advanced NLP design - full duplex speech with  
no switched loss on audio paths  
ST-BUS, GCI, or variable-rate SSI PCM interfaces  
Fast re-convergence time: tracks changing echo  
environment quickly  
User gain control provided for speaker path  
(-24 dB to +48 dB in 3 dB steps)  
Adaptation algorithm converges even during  
Double-Talk  
18 dB gain at Sout to compensate for high ERL  
environments  
Designed for exceptional performance in high  
background noise environments  
AGC on speaker path  
Handles up to 0 dB acoustic echo return loss  
Transparent data transfer and mute options  
20 MHz master clock operation  
Provides protection against narrow-band signal  
divergence  
Howling prevention stops uncontrolled oscillation  
in high loop gain conditions  
Low power mode during PCM Bypass  
Bootloadable for future factory software upgrades  
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs  
Offset nulling of all PCM channels  
Serial micro-controller interface  
Limiter  
S1  
S3  
S2  
+
µ/A-Law/  
Linear  
Linear/  
µ/A-Law  
ADV  
NLP  
18dB  
Gain  
Offset  
Null  
+
Sin  
Sout  
-
DATA1  
DATA2  
MD1  
Program  
RAM  
NBSD  
Micro  
Interface  
CONTROL  
UNIT  
Program  
ROM  
Adaptive  
Filter  
Double  
Talk  
Detector  
Howling  
Controller  
NBSD  
R1  
R3  
SCLK  
CS  
MD2  
Rout  
-24 -> +48dB  
R2  
Offset  
Null  
User  
Gain  
µ/A-Law/  
Linear  
Linear/  
µ/A-Law  
Rin  
AGC  
Limiter  
VSS  
VDD  
BCLK/C4i  
FORMAT  
ENA1  
MCLK  
RESET  
ENA2  
LAW  
F0i  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.  

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