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XRT91L31IQ-F PDF预览

XRT91L31IQ-F

更新时间： 2024-09-26 11:48:27
品牌 Logo 应用领域
艾科嘉 - EXAR ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
41页 884K
描述
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

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中文翻译

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XRT91L31IQ-F 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Transferred零件包装代码：QFP
包装说明：FQFP, QFP64,.51SQ,20针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：8.56Is Samacsys：N
应用程序：ATM;SDH;SONETJESD-30 代码：S-PQFP-G64
JESD-609代码：e3长度：10 mm
湿度敏感等级：3功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：FQFP封装等效代码：QFP64,.51SQ,20
封装形状：SQUARE封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：2.45 mm
子类别：ATM/SONET/SDH ICs最大压摆率：0.27 mA
标称供电电压：3.3 V表面贴装：YES
技术：CMOS电信集成电路类型：ATM/SONET/SDH TRANSCEIVER
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：10 mmBase Number Matches：1

XRT91L31IQ-F 数据手册

 浏览型号XRT91L31IQ-F的Datasheet PDF文件第2页浏览型号XRT91L31IQ-F的Datasheet PDF文件第3页浏览型号XRT91L31IQ-F的Datasheet PDF文件第4页浏览型号XRT91L31IQ-F的Datasheet PDF文件第5页浏览型号XRT91L31IQ-F的Datasheet PDF文件第6页浏览型号XRT91L31IQ-F的Datasheet PDF文件第7页 
XRT91L31  
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER  
JULY 2008  
REV. 1.0.2  
synchronize the transmit section timing. The device  
can internally monitor Loss of Signal (LOS) condition  
and automatically mute received data upon LOS. An  
on-chip SONET/SDH frame byte and boundary  
detector and frame pulse generator offers the ability  
recover SONET/SDH framing and to byte align the  
receive serial data stream into the 8-bit parallel bus.  
GENERAL DESCRIPTION  
The XRT91L31 is a fully integrated SONET/SDH  
transceiver for SONET/SDH 622.08 Mbps STS-12/  
STM-4 or 155.52 Mbps STS-3/STM-1 applications.  
The transceiver includes an on-chip Clock Multiplier  
Unit (CMU), which uses a high frequency Phase-  
Locked Loop (PLL) to generate the high-speed  
transmit serial clock from a slower external clock  
reference. It also provides Clock and Data Recovery  
(CDR) function by synchronizing its on-chip Voltage  
Controlled Oscillator (VCO) to the incoming serial  
data stream. The internal CDR unit can be disabled  
and bypassed in lieu of an externally recovered  
received clock from the optical module. Either the  
internally recovered clock or the externally recovered  
clock can be used for loop timing applications. The  
chip provides serial-to-parallel and parallel-to-serial  
converters using an 8-bit wide LVTTL system  
interface in both receive and transmit directions.  
The transmit section includes an option to accept a  
parallel clock signal from the framer/mapper to  
APPLICATIONS  
• SONET/SDH-based Transmission Systems  
• Add/Drop Multiplexers  
• Cross Connect Equipment  
• ATM and Multi-Service Switches, Routers and  
Switch/Routers  
• DSLAMS  
• SONET/SDH Test Equipment  
• DWDM Termination Equipment  
FIGURE 1. BLOCK DIAGRAM OF XRT91L31  
STS-12/STM-4 or STS-3/STM-1  
TRANSCEIVER  
PISO  
(Parallel Input  
Serial Output)  
TXOP/N  
TXDI[7:0]  
Re-Timer  
8
ENB  
ENB  
TXPCLK_IO  
Div by  
8
REFCLKP/N  
TTLREFCLK  
CMU  
RLOOPS  
ALOOP  
DLOOP  
CDRAUXREFCLK  
RXDO[7:0]  
SIPO  
(Serial Input  
Parallel Output)  
CDR  
RXIP/N  
8
XRXCLKIP/N  
Div by 8  
RXPCLKO  
Control Block  
Clock Control  
Loop Filters  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com  
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