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XRT91L82 PDF预览

XRT91L82

更新时间： 2024-02-24 20:40:53
品牌 Logo 应用领域
艾科嘉 - EXAR /
页数 文件大小 规格书
59页 391K
描述
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

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中文翻译

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XRT91L82 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：BGA, BGA196,14X14,40Reach Compliance Code：unknown
风险等级：5.81JESD-30 代码：S-PBGA-B196
JESD-609代码：e3端子数量：196
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA196,14X14,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1.8,3.3 V
认证状态：Not Qualified子类别：ATM/SONET/SDH ICs
最大压摆率：445 mA表面贴装：YES
电信集成电路类型：ATM/SONET/SDH TRANSCEIVER温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM

XRT91L82 数据手册

 浏览型号XRT91L82的Datasheet PDF文件第2页浏览型号XRT91L82的Datasheet PDF文件第3页浏览型号XRT91L82的Datasheet PDF文件第4页浏览型号XRT91L82的Datasheet PDF文件第5页浏览型号XRT91L82的Datasheet PDF文件第6页浏览型号XRT91L82的Datasheet PDF文件第7页 
xr  
PRELIMINARY  
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER  
XRT91L82  
APRIL 2005  
REV. P1.0.5  
of the FIFO_AUTORST register bit can automatically  
recover from an overflow condition. The operation of  
GENERAL DESCRIPTION  
The XRT91L82 is a fully integrated SONET/SDH  
transceiver for OC-48/STM16 applications supporting  
the use of Forward Error Correction (FEC) capability.  
The transceiver includes an on-chip Clock Multiplier  
Unit (CMU), which uses a high frequency Phase-  
Locked Loop (PLL) to generate the high-speed  
transmit serial clock from slower external clock  
references. It also provides Clock and Data Recovery  
(CDR) functions by synchronizing its on-chip Voltage  
Controlled Oscillator (VCO) to the incoming serial  
data stream. The chip provides serial-to-parallel and  
parallel-to-serial converters and 16-bit Differential  
LVDS/LVPECL, or Single-Ended LVPECL system  
interfaces in both receive and transmit directions.  
The transmit section includes a 16x9 Elastic Buffer  
(FIFO) to absorb any phase differences between the  
transmitter clock input and the internally generated  
transmitter reference clock. In the event of an  
overflow, an internal FIFO control circuit outputs an  
OVERFLOW indication. The FIFO under the control  
the device can be monitored by checking the status  
of the LOCKDET_CMU and LOCKDET_CDR output  
signals. An on-chip phase/frequency detector and  
charge-pump offers the ability to form a de-jittering  
PLL with an external VCXO that can be used in loop  
timing mode to clean up the recovered clock in the  
receive section.  
APPLICATIONS  
•
•
•
•
SONET/SDH-based Transmission Systems  
Add/Drop Multiplexers  
Cross Connect Equipment  
ATM and Multi-Service Switches, Routers and  
Switch/Routers  
•
•
•
DSLAMS  
SONET/SDH Test Equipment  
DWDM Termination Equipment  
F
IGURE 1. BLOCK  
D
IAGRAM OF XRT91L82  
STS-48 TRANSCEIVER  
WP  
OVERFLOW  
FIFO_RST  
TXOP/N  
PISO  
(Parallel Input  
Serial Output)  
Re-Timer  
TXDI[15:0]P/N  
TXSCLKOP/N  
16  
RP  
TXPCLKIP/N  
Div by  
16  
TXPCLKOP/N  
TXCLKO16P/N  
CMU  
TXCLKO16SEL  
DLOOP RLOOPS  
RLOOPP  
SIPO  
(Serial Input  
Parallel Output)  
RXDO[15:0]P/N  
RXPCLKOP/N  
CDR  
RXIP/N  
16  
Div by  
16  
DISRD  
DISRDCLK  
TDO  
TDI  
TCK  
TMS  
TRST  
PFD  
& Charge Pump  
Serial  
Microprocessor  
Hardware  
Control  
JTAG  
Exar Corporation 48720 Kato Road, Fremont CA, 94538  
•
(510) 668-7000  
•
FAX (510) 668-7017  
•
www.exar.com  
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