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XRT91L34IV-F PDF预览

XRT91L34IV-F

更新时间: 2024-02-21 13:03:18
品牌 Logo 应用领域
艾科嘉 - EXAR /
页数 文件大小 规格书
38页 404K
描述
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

XRT91L34IV-F 数据手册

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XRT91L34  
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR  
OCTOBER 2007  
REV. 1.0.1  
attempts to lock onto the incoming receive serial data  
GENERAL DESCRIPTION  
stream. Whenever the recovered clock frequency  
deviates from the local reference clock frequency by  
more than approximately ±500 ppm, the clock  
recovery PLL will switch and lock back onto the local  
reference clock and declare a Loss of Lock.  
Whenever a Loss of Lock or a Loss of Signal event  
occurs, the CDR will continue to supply a recovered  
clock (based on the local reference) to the framer/  
mapper device. When the SDEXT is de-asserted by  
the optical module or when internal DLOS is  
asserted, the receive serial data output will be forced  
to a logic zero state for the entire duration that a LOS  
condition is declared. This acts as a receive data  
mute upon LOS function to prevent random noise  
from being misinterpreted as valid incoming data.  
When the SDEXT becomes active and the recovered  
clock is determined to be within ±500 ppm accuracy  
with respect to the local reference source and LOS is  
no longer declared, the clock recovery PLL will switch  
and lock back onto the incoming receive serial data  
stream. Figure 1 shows the block diagram of the  
XRT91L34.  
The XRT91L34 is a fully integrated quad channel  
multirate Clock and Data Recovery (CDR) device for  
SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52  
Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0  
applications. The device provides Clock and Data  
Recovery (CDR) function by synchronizing its on-chip  
Voltage Controlled Oscillator (VCO) to the incoming  
serial data stream. The device internally monitors  
Loss of Lock (LOL) conditions and automatically  
mutes recovered data upon Loss of Signal (LOS)  
conditions.  
C
LOCK AND DATA RECOVERY OVERVIEW  
The clock and data recovery (CDR) unit accepts the  
high speed NRZ serial data from the LVDS or  
Differential LVPECL receiver and generates a clock  
that is the same frequency as the incoming data. The  
CDR block uses a reference clock to train and  
monitor its clock recovery PLL. All four channels  
share a single 77.76MHz or 19.44MHz reference  
clock. Upon startup, the PLL locks to the local  
reference clock. Once this is achieved, the PLL  
FIGURE 1. BLOCK  
D
IAGRAM OF XRT91L34  
TEST  
RESET  
OUTCFG  
HOST /HW  
XRT91L34  
0
CDRREFSEL  
DLOSDIS  
DLOSDIS /SDI  
SDI  
REFCLKP  
REFCLKN  
Global Control Block  
1
19.44 / 77.76 MHz  
Serial Proccesor  
INT  
TTLREFCLK  
Interface  
CS  
LVDS/LVPECL LEVEL SELECT  
RCLKDIS0  
SCLK  
SDO  
LVDS/LVPECL  
Output Drivers  
LVDS/LVPECL  
Input Drivers  
RECVD-  
DATAOUT  
RXDI0P  
RXDI0N  
RXDO0P  
RXDO0N  
0
RXDATAIN  
100  
CDR  
1
STS-12/3/1  
or  
STM-4/1/0  
Clock and Data  
Recovery  
RECVD-  
0
RXCLKO0P  
RXCLKO0N  
CLKOUT  
RX LOOP  
FILTER  
1
HOST MODE  
ONLY  
DLOSDIS  
DLOS  
LOL0  
Channel Control Block  
CDRDIS0  
DATA0RATE1  
DATA0RATE0  
SDEXT0  
POL0  
Channel 0  
Channel 1  
Channel 2  
Channel 3  
Exar Corporation 48720 Kato Road, Fremont CA, 94538  
(510) 668-7000  
FAX (510) 668-7017 www.exar.com  

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