Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> XRT91L34IV-F

XRT91L34IV-F

更新时间： 2024-02-01 02:33:49

品牌	Logo	应用领域
艾科嘉 - EXAR		/
页数	文件大小	规格书
38页	404K
描述
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

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XRT91L34IV-F 数据手册

XRT91L34

QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR

OCTOBER 2007

REV. 1.0.1

attempts to lock onto the incoming receive serial data

GENERAL DESCRIPTION

stream. Whenever the recovered clock frequency

deviates from the local reference clock frequency by

more than approximately ±500 ppm, the clock

recovery PLL will switch and lock back onto the local

reference clock and declare a Loss of Lock.

Whenever a Loss of Lock or a Loss of Signal event

occurs, the CDR will continue to supply a recovered

clock (based on the local reference) to the framer/

mapper device. When the SDEXT is de-asserted by

the optical module or when internal DLOS is

asserted, the receive serial data output will be forced

to a logic zero state for the entire duration that a LOS

condition is declared. This acts as a receive data

mute upon LOS function to prevent random noise

from being misinterpreted as valid incoming data.

When the SDEXT becomes active and the recovered

clock is determined to be within ±500 ppm accuracy

with respect to the local reference source and LOS is

no longer declared, the clock recovery PLL will switch

and lock back onto the incoming receive serial data

stream. Figure 1 shows the block diagram of the

XRT91L34.

The XRT91L34 is a fully integrated quad channel

multirate Clock and Data Recovery (CDR) device for

SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52

Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0

applications. The device provides Clock and Data

Recovery (CDR) function by synchronizing its on-chip

Voltage Controlled Oscillator (VCO) to the incoming

serial data stream. The device internally monitors

Loss of Lock (LOL) conditions and automatically

mutes recovered data upon Loss of Signal (LOS)

conditions.

LOCK AND DATA RECOVERY OVERVIEW

The clock and data recovery (CDR) unit accepts the

high speed NRZ serial data from the LVDS or

Differential LVPECL receiver and generates a clock

that is the same frequency as the incoming data. The

CDR block uses a reference clock to train and

monitor its clock recovery PLL. All four channels

share a single 77.76MHz or 19.44MHz reference

clock. Upon startup, the PLL locks to the local

reference clock. Once this is achieved, the PLL

FIGURE 1. BLOCK

IAGRAM OF XRT91L34

TEST

RESET

OUTCFG

HOST /HW

XRT91L34

CDRREFSEL

DLOSDIS

DLOSDIS /SDI

SDI

REFCLKP

REFCLKN

Global Control Block

19.44 / 77.76 MHz

Serial Proccesor

INT

TTLREFCLK

Interface

LVDS/LVPECL LEVEL SELECT

RCLKDIS0

SCLK

SDO

LVDS/LVPECL

Output Drivers

LVDS/LVPECL

Input Drivers

RECVD-

DATAOUT

RXDI0P

RXDI0N

RXDO0P

RXDO0N

RXDATAIN

100

CDR

STS-12/3/1

STM-4/1/0

Clock and Data

Recovery

RECVD-

RXCLKO0P

RXCLKO0N

CLKOUT

RX LOOP

FILTER

HOST MODE

ONLY

DLOSDIS

DLOS

LOL0

Channel Control Block

CDRDIS0

DATA0RATE1

DATA0RATE0

SDEXT0

POL0

Channel 0

Channel 1

Channel 2

Channel 3

Exar Corporation 48720 Kato Road, Fremont CA, 94538

•

(510) 668-7000

•

FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...38

中文翻译

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与XRT91L34IV-F相关器件

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XRT91L80	EXAR	获取价格	2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80_0507	EXAR	获取价格	2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80IB	EXAR	获取价格	2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80IB-F	EXAR	获取价格	Telecom IC
XRT91L81	EXAR	获取价格	2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB	EXAR	获取价格	2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82	EXAR	获取价格	2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82IB	EXAR	获取价格	2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT94L31	EXAR	获取价格	3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
XRT94L31_07	EXAR	获取价格	3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC

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