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XRT91L80_0507 PDF预览

XRT91L80_0507

更新时间: 2024-01-28 15:26:13
品牌 Logo 应用领域
艾科嘉 - EXAR /
页数 文件大小 规格书
45页 335K
描述
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

XRT91L80_0507 数据手册

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PRELIMINARY  
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER  
XRT91L80  
JULY 2005  
REV. P1.1.0  
control of the FIFO_AUTORST pin can automatically  
recover from an overflow condition. The operation of  
GENERAL DESCRIPTION  
The XRT91L80 is a fully integrated SONET/SDH  
transceiver for SONET OC-48/STM-16 applications  
supporting the use of Forward Error Correction (FEC)  
capability. The transceiver includes an on-chip Clock  
Multiplier Unit (CMU), which uses a high frequency  
Phase-Locked Loop (PLL) to generate the high-  
speed transmit serial clock from a slower external  
clock reference. It also provides Clock and Data  
Recovery (CDR) functions by synchronizing its on-  
chip Voltage Controlled Oscillator (VCO) to the  
incoming serial data stream. The chip provides serial-  
to-parallel and parallel-to-serial converters and 4-bit  
LVDS system interfaces in both receive and transmit  
directions. The transmit section includes a 4x9 Elastic  
Buffer (FIFO) to absorb any phase differences  
between the transmitter clock input and the internally  
generated transmitter reference clock. In the event of  
an overflow, an internal FIFO control circuit outputs  
an OVERFLOW indication. The FIFO under the  
the device can be monitored by checking the status  
of the LOCKDET_CMU, LOCKDET_CDR, and  
LOSDET output signals. An on-chip phase/frequency  
detector and charge-pump offers the ability to form a  
de-jittering PLL with an external VCXO that can be  
used in loop timing mode to clean up the recovered  
clock in the receive section.  
APPLICATIONS  
SONET/SDH-based Transmission Systems  
Add/Drop Multiplexers  
Cross Connect Equipment  
ATM and Multi-Service Switches and Routers  
DSLAMS  
SONET/SDH Test Equipment  
DWDM Termination Equipment  
F
IGURE 1. BLOCK  
D
IAGRAM OF XRT91L80  
STS-48 TRANSCEIVER  
WP  
FIFO_RST  
FIFO_AUTORST  
TXDI0P/N  
TXDI1P/N  
TXDI2P/N  
TXDI3P/N  
PISO  
(Parallel Input  
Serial Output)  
TXOP/N  
Re-Timer  
RP  
TXPCLKIP/N  
TXPCLKOP/N  
TXCLKO16P/N  
Div by 4  
Div by 16  
CMU  
TXCLKO16DIS  
DLOOP RLOOPS  
RLOOPP  
RXDO0P/N  
RXDO1P/N  
RXDO2P/N  
RXDO3P/N  
SIPO  
(Serial Input  
Parallel Output)  
CDR  
RXIP/N  
RXPCLKOP/N  
RXCLKO16P/N  
Div by 4  
Div by 16  
LOSDMUTE  
DISRD  
TDO  
TDI  
TCK  
TMS  
TRST  
PFD  
& Charge Pump  
Serial  
Microprocessor  
Hardware  
Control  
JTAG  
Exar Corporation 48720 Kato Road, Fremont CA, 94538  
(510) 668-7000  
FAX (510) 668-7017  
www.exar.com  

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