Datasheet > XRT91L30_0611

XRT91L30_0611

更新时间： 2024-09-26 03:52:55

品牌	Logo	应用领域
艾科嘉 - EXAR		/
页数	文件大小	规格书
39页	754K
描述
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

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数据手册

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XRT91L30_0611 数据手册

XRT91L30

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

DECEMBER 2006

REV. 1.0.1

parallel clock signal from the framer/mapper to

synchronize the transmit section timing. The device

GENERAL DESCRIPTION

The XRT91L30 is a fully integrated SONET/SDH

transceiver for SONET/SDH 622.08 Mbps STS-12/

STM-4 or 155.52 Mbps STS-3/STM-1 applications.

The transceiver includes an on-chip Clock Multiplier

Unit (CMU), which uses a high frequency Phase-

Locked Loop (PLL) to generate the high-speed

transmit serial clock from a slower external clock

reference. It also provides Clock and Data Recovery

(CDR) function by synchronizing its on-chip Voltage

Controlled Oscillator (VCO) to the incoming serial

data stream. The internal CDR unit can be disabled

and bypassed in lieu of an externally recovered

received clock from the optical module. Either the

internally recovered clock or the externally recovered

clock can be used for loop timing applications. The

chip provides serial-to-parallel and parallel-to-serial

converters using an 8-bit wide LVTTL system

interface in both receive and transmit directions.

The transmit section includes an option to accept a

can internally monitor Loss of Signal (LOS) condition

and automatically mute received data upon LOS. An

on-chip SONET/SDH frame byte and boundary

detector and frame pulse generator offers the ability

recover SONET/SDH framing and to byte align the

receive serial data stream into the 8-bit parallel bus.

APPLICATIONS

• SONET/SDH-based Transmission Systems

• Add/Drop Multiplexers

• Cross Connect Equipment

• ATM and Multi-Service Switches, Routers and

Switch/Routers

• DSLAMS

• SONET/SDH Test Equipment

• DWDM Termination Equipment

FIGURE 1. BLOCK DIAGRAM OF XRT91L30

STS-12/STM-4 or STS-3/STM-1

TRANSCEIVER

PISO

(Parallel Input

Serial Output)

TXOP/N

TXDI[7:0]

Re-Timer

ENB

TXPCLK_IO

Div by

REFCLKP/N

TTLREFCLK

CMU

RLOOPS

ALOOP

DLOOP

CDRAUXREFCLK

RXDO[7:0]

SIPO

(Serial Input

Parallel Output)

CDR

RXIP/N

XRXCLKIP/N

Div by 8

RXPCLKO

Control Block

Clock Control

Loop Filters

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...39

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