XMC7000 microcontroller
32-bit Arm® Cortex®-M7
Table of contents
Table of contents
General description .......................................................................................................................... 1
Features .......................................................................................................................................... 1
Table of contents.............................................................................................................................. 5
1 Features list .................................................................................................................................. 7
1.1 Communication peripheral instance list .............................................................................................................. 9
2 Blocks and functionality................................................................................................................10
Block diagram.................................................................................................................................10
3 Functional description ..................................................................................................................11
3.1 CPU subsystem .................................................................................................................................................... 11
3.1.1 CPU.................................................................................................................................................... 11
3.1.2 DMA controllers.................................................................................................................................. 11
3.1.3 Flash................................................................................................................................................... 11
3.1.4 SRAM................................................................................................................................................. 11
3.1.5 ROM................................................................................................................................................... 11
3.1.6 Cryptography accelerator for security ................................................................................................ 11
3.2 System resources................................................................................................................................................. 12
3.2.1 Power system..................................................................................................................................... 12
3.2.2 Regulators.......................................................................................................................................... 12
3.2.3 Clock system...................................................................................................................................... 14
3.2.4 Reset.................................................................................................................................................. 15
3.2.5 Watchdog timer .................................................................................................................................. 15
3.2.6 Power modes ..................................................................................................................................... 15
3.3 Peripherals ........................................................................................................................................................... 16
3.3.1 Peripheral clock dividers .................................................................................................................... 16
3.3.2 Peripheral protection unit ................................................................................................................... 16
3.3.3 12-bit SAR ADC ................................................................................................................................. 16
3.3.4 Timer/counter/PWM block (TCPWM)................................................................................................. 17
3.3.5 Serial communication blocks (SCB)................................................................................................... 17
3.3.6 CAN FD.............................................................................................................................................. 18
3.3.7 Ethernet MAC..................................................................................................................................... 18
3.3.8 External memory interface ................................................................................................................. 18
3.3.9 SDHC interface .................................................................................................................................. 18
3.3.10 Audio interface ................................................................................................................................. 18
3.3.11 One-time-programmable (OTP) eFuse ............................................................................................ 18
3.3.12 Event generator................................................................................................................................ 18
3.3.13 Trigger multiplexer............................................................................................................................ 19
3.4 I/Os........................................................................................................................................................................ 19
3.4.1 Port nomenclature.............................................................................................................................. 19
3.4.2 GPIO standard (GPIO_STD).............................................................................................................. 19
3.4.3 GPIO enhanced (GPIO_ENH)............................................................................................................ 19
3.4.4 HSIO standard (HSIO_STD) .............................................................................................................. 20
3.4.5 Smart I/O............................................................................................................................................ 20
4 XMC7200 address map...................................................................................................................21
5 Flash base address map.................................................................................................................23
6 Peripheral I/O map........................................................................................................................24
7 XMC7200 clock diagram.................................................................................................................26
8 XMC7200 CPU start-up sequence ....................................................................................................27
9 Pin assignment .............................................................................................................................28
10 High-speed I/O matrix connections...............................................................................................31
11 Package pin list and alternate functions .......................................................................................32
12 Power pin assignments................................................................................................................40
13 Alternate function pin assignments ..............................................................................................41
13.1 Pin function description .................................................................................................................................... 49
Datasheet
5
002-33522 Rev. *B
2022-10-21
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