Datasheet > XC2C384-10FT256C

XC2C384-10FT256C

更新时间： 2024-11-08 19:23:35

品牌	Logo	应用领域
赛灵思 - XILINX		输入元件可编程逻辑
页数	文件大小	规格书
26页	297K
描述
Flash PLD, 10ns, 384-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FTBGA-256

阅读下载

中文翻译

获取价格

技术参数
数据手册
替代型号

如果您发现信息不准确，欢迎纠错

XC2C384-10FT256C 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA, BGA256,16X16,40	针数：	256
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.D
HTS代码：	8542.39.00.01	风险等级：	5.2
其他特性：	YES	系统内可编程：	YES
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
JTAG BST：	YES	长度：	17 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	212	宏单元数：	384
端子数量：	256	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 212 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA256,16X16,40
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	240	电源：	1.5/3.3,1.8 V
可编程逻辑类型：	FLASH PLD	传播延迟：	10 ns
认证状态：	Not Qualified	座面最大高度：	1.55 mm
子类别：	Programmable Logic Devices	最大供电电压：	1.9 V
最小供电电压：	1.7 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	17 mm	Base Number Matches：	1

XC2C384-10FT256C 数据手册

XC2C384 CoolRunner-II CPLD

DS095 (v3.2) March 8, 2007

Product Specification

Features

Description

•

Optimized for 1.8V systems

The CoolRunner-II 384-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

As fast as 7.1 ns pin-to-pin delays

As low as 14 μA quiescent current

•

Industry’s best 0.18 micron CMOS CPLD

Optimized architecture for effective logic synthesis

Multi-voltage I/O operation — 1.5V to 3.3V

This device consists of twenty four Function Blocks

inter-connected by a low power Advanced Interconnect

Matrix (AIM). The AIM feeds 40 true and complement inputs

to each Function Block. The Function Blocks consist of a 40

by 56 P-term PLA and 16 macrocells which contain numer-

ous configuration bits that allow for combinational or regis-

tered modes of operation.

Available in multiple package options

144-pin TQFP with 118 user I/O

208-pin PQFP with 173 user I/O

256-ball FT (1.0mm) BGA with 212 user I/O

324-ball FG (1.0mm) BGA with 240 user I/O

Pb-free available for all packages

•

Advanced system features

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt-trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as direct input registers to store signals directly

from input pins.

Fastest in system programming

1.8V ISP using IEEE 1532 (JTAG) interface

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

Unsurpassed low power management

DataGATE enable (DGE) signal control

Four separate I/O banks

RealDigital 100% CMOS product term generation

Flexible clocking modes

Optional DualEDGE triggered registers

Clock divider (divide by 2,4,6,8,10,12,14,16)

CoolCLOCK

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asynchro-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

Global signal options with macrocell control

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

Advanced design security

PLA architecture

Superior pinout retention

100% product term routability across function

block

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Open-drain output option for Wired-OR and LED

drive

Optional bus-hold, 3-state or weak pullup on

selected I/O pins

Optional configurable grounds on unused I/Os

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

Circuitry has also been included to divide one externally

supplied global clock (GCK2) by eight different selections.

This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE

flip-flop gives the resultant CoolCLOCK feature.

SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility

Hot pluggable

DataGATE is a method to selectively disable inputs of the

CPLD that are not of interest during certain points in time.

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS095 (v3.2) March 8, 2007

www.xilinx.com

Product Specification

12 3 4 5 6 7...26

中文翻译

下载PDF

XC2C384-10FT256C 替代型号

型号	品牌	替代类型	描述	数据表
XC2C384-10FT256I	XILINX	完全替代	Flash PLD, 10ns, 384-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FTBGA-256
XC2C384-10FTG256C	XILINX	完全替代	Flash PLD, 10ns, 384-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FTBGA-256
XC2C384-10FTG256I	XILINX	完全替代	Flash PLD, 10ns, 384-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FTBGA-256

与XC2C384-10FT256C相关器件

型号	品牌	获取价格	描述	数据表
XC2C384-10FT256I	XILINX	获取价格	Flash PLD, 10ns, 384-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FTBGA-256
XC2C384-10FTG256C	XILINX	获取价格	Flash PLD, 10ns, 384-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FTBGA-256
XC2C384-10FTG256I	XILINX	获取价格	Flash PLD, 10ns, 384-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FTBGA-256
XC2C384-10PQ208C	XILINX	获取价格	暂无描述
XC2C384-10PQG208C	XILINX	获取价格	暂无描述
XC2C384-10TQ144C	XILINX	获取价格	暂无描述
XC2C384-10TQ144I	XILINX	获取价格	Flash PLD, 10ns, 384-Cell, CMOS, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144
XC2C384-10TQG144C	XILINX	获取价格	暂无描述
XC2C384-10TQG144I	XILINX	获取价格	暂无描述
XC2C384-7FGG324C	XILINX	获取价格	Flash PLD, 7.5ns, 384-Cell, CMOS, PBGA324, 23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-324

与XC2C384-10FT256C相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

17
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

XC2C384-10FT256C

XC2C384-10FT256C 技术参数

XC2C384-10FT256C 数据手册

XC2C384-10FT256C 替代型号

与XC2C384-10FT256C相关器件

与XC2C384-10FT256C相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

XC2C384-10FT256C

XC2C384-10FT256C 技术参数

XC2C384-10FT256C 数据手册

XC2C384-10FT256C 替代型号

与XC2C384-10FT256C相关器件

与XC2C384-10FT256C相关文章

您还可以找

您在本页遇到什么问题？