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XC18V01SOG20C0936

更新时间： 2024-11-11 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 光电二极管内存集成电路
页数 文件大小 规格书
24页 316K
描述
Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PDSO20, SOIC-20

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XC18V01SOG20C0936 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：20
Reach Compliance Code：compliantECCN代码：3A991.B.1
HTS代码：8542.32.00.61风险等级：5.58
最长访问时间：15 nsJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：12.8 mm
内存密度：1048576 bit内存集成电路类型：CONFIGURATION MEMORY
内存宽度：8湿度敏感等级：3
功能数量：1端子数量：20
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL/SERIAL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2.65 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.5 mm
Base Number Matches：1

XC18V01SOG20C0936 数据手册

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24  
R
XC18V00 Series In-System-Programmable  
Configuration PROMs  
0
DS026 (v5.2) January 11, 2008  
Product Specification  
Features  
•
In-System Programmable 3.3V PROMs for  
Configuration of Xilinx FPGAs  
•
•
Low-Power Advanced CMOS FLASH Process  
Dual Configuration Modes  
♦
♦
Endurance of 20,000 Program/Erase Cycles  
♦
♦
Serial Slow/Fast Configuration (up to 33 MHz)  
Parallel (up to 264 Mb/s at 33 MHz)  
Program/Erase Over Full Industrial Voltage and  
Temperature Range (–40°C to +85°C)  
•
•
•
5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals  
3.3V or 2.5V Output Capability  
•
•
IEEE Std 1149.1 Boundary-Scan (JTAG) Support  
JTAG Command Initiation of Standard FPGA  
Configuration  
Design Support Using the Xilinx ISE™ Foundation™  
Software Packages  
•
•
Simple Interface to the FPGA  
•
•
Available in PC20, SO20, PC44, and VQ44 Packages  
Lead-Free (Pb-Free) Packaging  
Cascadable for Storing Longer or Multiple Bitstreams  
Description  
Xilinx introduces the XC18V00 series of in-system  
programmable configuration PROMs (Figure 1). Devices in  
this 3.3V family include a 4-megabit, a 2-megabit, a  
1-megabit, and a 512-kilobit PROM that provide an easy-to-  
use, cost-effective method for reprogramming and storing  
Xilinx FPGA configuration bitstreams.  
When the FPGA is in Master SelectMAP mode, the FPGA  
generates a configuration clock that drives the PROM. When  
the FPGA is in Slave Parallel or Slave SelectMAP mode, an  
external oscillator generates the configuration clock that  
drives the PROM and the FPGA. After CE and OE are  
enabled, data is available on the PROM’s DATA (D0-D7)  
pins. New data is available a short access time after each  
rising clock edge. The data is clocked into the FPGA on the  
following rising edge of the CCLK. A free-running oscillator  
can be used in the Slave Parallel or Slave SelecMAP modes.  
When the FPGA is in Master Serial mode, it generates a  
configuration clock that drives the PROM. A short access  
time after CE and OE are enabled, data is available on the  
PROM DATA (D0) pin that is connected to the FPGA DIN  
pin. New data is available a short access time after each  
rising clock edge. The FPGA generates the appropriate  
number of clock pulses to complete the configuration. When  
the FPGA is in Slave Serial mode, the PROM and the FPGA  
are clocked by an external clock.  
Multiple devices can be cascaded by using the CEO output  
to drive the CE input of the following device. The clock  
inputs and the DATA outputs of all PROMs in this chain are  
interconnected. All devices are compatible and can be  
cascaded with other members of the family or with the  
XC17V00 one-time programmable serial PROM family.  
X-Ref Target - Figure 1  
CLK CE  
OE/RESET  
TCK  
TMS  
TDI  
CEO  
Data  
Control  
and  
JTAG  
Serial  
or  
Parallel  
Interface  
Data  
D0 DATA  
Serial or Parallel Mode  
Memory  
Address  
Interface  
7
D[1:7]  
Parallel Interface  
TDO  
CF  
DS026_01_040204  
Figure 1: XC18V00 Series Block Diagram  
© 1999–2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other  
trademarks are the property of their respective owners.  
DS026 (v5.2) January 11, 2008  
www.xilinx.com  
Product Specification  
1
1234567...24

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