5秒后页面跳转
捷配首页

Datasheet > XC18V01VQ44C0799
XC18V01VQ44C0799 PDF预览

XC18V01VQ44C0799

更新时间： 2024-11-11 14:45:39
品牌 Logo 应用领域
赛灵思 - XILINX 内存集成电路
页数 文件大小 规格书
19页 218K
描述
Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44

阅读下载

中文翻译

获取价格

XC18V01VQ44C0799 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP,针数：44
Reach Compliance Code：unknownECCN代码：3A001.B.1.A
HTS代码：8542.39.00.01风险等级：5.5
最长访问时间：15 nsJESD-30 代码：S-PQFP-G44
长度：10 mm内存密度：1048576 bit
内存集成电路类型：CONFIGURATION MEMORY内存宽度：8
功能数量：1端子数量：44
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX8
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE
并行/串行：PARALLEL/SERIAL认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
宽度：10 mmBase Number Matches：1

XC18V01VQ44C0799 数据手册

 浏览型号XC18V01VQ44C0799的Datasheet PDF文件第2页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第3页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第4页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第5页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第6页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第7页 
0
XC18V00 Series of In-System  
Programmable Configuration  
PROMs  
R
0
0
DS026 (v3.0) November 12, 2001  
Product Specification  
•
Dual configuration modes  
Features  
-
-
Serial Slow/Fast configuration (up to 33 MHz)  
Parallel (up to 264 Mb/s at 33 MHz)  
•
In-system programmable 3.3V PROMs for  
configuration of Xilinx FPGAs  
•
•
•
•
5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals  
3.3V or 2.5V output capability  
-
-
Endurance of 20,000 program/erase cycles  
Program/erase over full commercial/industrial  
voltage and temperature range  
Available in PC20, SO20, PC44 and VQ44 packages  
•
•
•
•
IEEE Std 1149.1 boundary-scan (JTAG) support  
Simple interface to the FPGA  
Design support using the Xilinx Alliance and  
Foundation series software packages.  
•
JTAG command initiation of standard FPGA  
configuration  
Cascadable for storing longer or multiple bitstreams  
Low-power advanced CMOS FLASH process  
Description  
Xilinx introduces the XC18V00 series of in-system program-  
mable configuration PROMs (Figure 1). Initial devices in this  
3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a  
When the FPGA is in Slave-Parallel or SelectMAP Mode, an  
external oscillator generates the configuration clock that  
drives the PROM and the FPGA. After the rising CCLK  
edge, data are available on the PROMs DATA (D0-D7) pins.  
The data is clocked into the FPGA on the following rising  
edge of the CCLK. Neither Slave-Parallel nor SelectMAP  
utilize a Length Count, so a free-running oscillator can be  
used.  
512-Kbit, and  
a
256-Kbit PROM that provide an  
easy-to-use, cost-effective method for re-programming and  
storing large Xilinx FPGA or CPLD configuration bitstreams.  
When the FPGA is in Master Serial mode, it generates a  
configuration clock that drives the PROM. A short access  
time after the rising CCLK, data is available on the PROM  
DATA (D0) pin that is connected to the FPGA DIN pin. The  
FPGA generates the appropriate number of clock pulses to  
complete the configuration. When the FPGA is in Slave  
Serial mode, the PROM and the FPGA are clocked by an  
external clock.  
Multiple devices can be concatenated by using the CEO  
output to drive the CE input of the following device. The  
clock inputs and the DATA outputs of all PROMs in this  
chain are interconnected. All devices are compatible and  
can be cascaded with other members of the family or with  
the XC17V00 one-time programmable Serial PROM family.  
OE/Reset  
CLK CE  
TCK  
Data  
Control  
CEO  
Serial  
or  
Parallel  
Interface  
TMS  
TDI  
and  
JTAG  
Interface  
Memory  
D0 DATA  
(Serial or Parallel  
[Slave-Parallel/SelectMAP] Mode)  
Data  
Address  
TDO  
7
D[1:7]  
Slave-Parallel and  
SelectMAP Interface  
CF  
DS026_01_111201  
Figure 1: XC18V00 Series Block Diagram  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS026 (v3.0) November 12, 2001  
www.xilinx.com  
1
Product Specification  
1-800-255-7778  
 
1234567...19

中文翻译

下载PDF

与XC18V01VQ44C0799相关器件

型号 品牌 获取价格 描述 数据表
XC18V01VQ44C0901 XILINX

获取价格

 		Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44
XC18V01VQ44C0936 XILINX

获取价格

 		Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44
XC18V01VQ44I ETC

获取价格

 		Sequential Access Serial EEPROM
XC18V01VQG44C XILINX

获取价格

 		In-System-Programmable Configuration PROMs
XC18V01VQG44C0936 XILINX

获取价格

 		Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44
XC18V02PC20 XILINX

获取价格

 		In-System Programmable Configuration PROMs
XC18V02PC20C XILINX

获取价格

 		In-System Programmable Configuration PROMs
XC18V02PC44 XILINX

获取价格

 		In-System Programmable Configuration PROMs
XC18V02PC44C XILINX

获取价格

 		In-System Programmable Configuration PROMs
XC18V02PC44C0799 XILINX

获取价格

 		Configuration Memory, 256KX8, 20ns, Parallel/serial, CMOS, PQCC44, PLASTIC, LCC-44

与XC18V01VQ44C0799相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证