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XC18V00 Series In-System
Programmable Configuration
PROMs
R
0
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DS026 (v4.0) June 11, 2003
Product Specification
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Dual configuration modes
Features
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-
Serial Slow/Fast configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)
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In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
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-
Endurance of 20,000 program/erase cycles
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5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
3.3V or 2.5V output capability
Program/erase over full commercial/industrial
voltage and temperature range (–40°C to +85°C)
Available in PC20, SO20, PC44, and VQ44 packages
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•
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IEEE Std 1149.1 boundary-scan (JTAG) support
Simple interface to the FPGA
Design support using the Xilinx Alliance and
Foundation series software packages.
Cascadable for storing longer or multiple bitstreams
Low-power advanced CMOS FLASH process
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JTAG command initiation of standard FPGA
configuration
When the FPGA is in Master-SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM.
When the FPGA is in Slave-Parallel or Slave-SelectMAP
Mode, an external oscillator generates the configuration
clock that drives the PROM and the FPGA. After CE and
OE are enabled, data is available on the PROMs DATA
(D0-D7) pins. New data is available a short access time
after each rising clock edge. The data is clocked into the
FPGA on the following rising edge of the CCLK. A free-run-
ning oscillator can be used in the Slave-Parallel or
Slave-SelecMAP modes.
Description
Xilinx introduces the XC18V00 series of in-system program-
mable configuration PROMs (Figure 1). Devices in this 3.3V
family include a 4-megabit, a 2-megabit, a 1-megabit, and a
512-kilobit PROM that provide an easy-to-use, cost-effec-
tive method for re-programming and storing Xilinx FPGA
configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE and OE are enabled, data is available on the
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC17V00 one-time programmable Serial PROM family.
PROM DATA (D0) pin that is connected to the FPGA D
IN
pin. New data is available a short access time after each ris-
ing clock edge. The FPGA generates the appropriate num-
ber of clock pulses to complete the configuration. When the
FPGA is in Slave Serial mode, the PROM and the FPGA
are clocked by an external clock.
CLK CE
OE/Reset
TCK
Data
Control
CEO
Serial
or
Parallel
Interface
TMS
TDI
and
JTAG
Interface
Memory
D0 DATA
Serial or Parallel Mode
Data
Address
TDO
7
D[1:7]
Parallel Interface
CF
DS026_01_090502
Figure 1: XC18V00 Series Block Diagram
©2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you
may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any war-
ranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS026 (v4.0) June 11, 2003
www.xilinx.com
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Product Specification
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