Datasheet > XC18V00SERIES

XC18V00SERIES

更新时间： 2024-11-10 23:30:31

品牌	Logo	应用领域
其他 - ETC		可编程只读存储器
页数	文件大小	规格书
19页	235K
描述
In-System Programmable Configuration PROMs

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XC18V00SERIES 数据手册

XC18V00 Series of In-System

Programmable Configuration

PROMs

DS026 (v3.0) November 12, 2001

Product Specification

•

Dual configuration modes

Features

Serial Slow/Fast configuration (up to 33 MHz)

Parallel (up to 264 Mb/s at 33 MHz)

•

In-system programmable 3.3V PROMs for

configuration of Xilinx FPGAs

•

5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals

3.3V or 2.5V output capability

Endurance of 20,000 program/erase cycles

Program/erase over full commercial/industrial

voltage and temperature range

Available in PC20, SO20, PC44 and VQ44 packages

•

IEEE Std 1149.1 boundary-scan (JTAG) support

Simple interface to the FPGA

Design support using the Xilinx Alliance and

Foundation series software packages.

•

JTAG command initiation of standard FPGA

configuration

Cascadable for storing longer or multiple bitstreams

Low-power advanced CMOS FLASH process

Description

Xilinx introduces the XC18V00 series of in-system program-

mable configuration PROMs (Figure 1). Initial devices in this

3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a

When the FPGA is in Slave-Parallel or SelectMAP Mode, an

external oscillator generates the configuration clock that

drives the PROM and the FPGA. After the rising CCLK

edge, data are available on the PROMs DATA (D0-D7) pins.

The data is clocked into the FPGA on the following rising

edge of the CCLK. Neither Slave-Parallel nor SelectMAP

utilize a Length Count, so a free-running oscillator can be

used.

512-Kbit, and

256-Kbit PROM that provide an

easy-to-use, cost-effective method for re-programming and

storing large Xilinx FPGA or CPLD configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising CCLK, data is available on the PROM

DATA (D0) pin that is connected to the FPGA D_INpin. The

FPGA generates the appropriate number of clock pulses to

complete the configuration. When the FPGA is in Slave

Serial mode, the PROM and the FPGA are clocked by an

external clock.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family or with

the XC17V00 one-time programmable Serial PROM family.

OE/Reset

CLK CE

TCK

Data

Control

CEO

Serial

Parallel

Interface

TMS

TDI

and

JTAG

Interface

Memory

D0 DATA

(Serial or Parallel

[Slave-Parallel/SelectMAP] Mode)

Data

Address

TDO

D[1:7]

Slave-Parallel and

SelectMAP Interface

DS026_01_111201

Figure 1: XC18V00 Series Block Diagram

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS026 (v3.0) November 12, 2001

www.xilinx.com

Product Specification

1-800-255-7778

12 3 4 5 6 7...19

中文翻译

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与XC18V00SERIES相关器件

型号	品牌	获取价格	描述	数据表
XC18V01PC20	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01PC20C	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01PC20C0901	XILINX	获取价格	Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20
XC18V01PC20C0936	XILINX	获取价格	Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20
XC18V01PC20I	ETC	获取价格	Sequential Access Serial EEPROM
XC18V01PC44	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01PC44C	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01PCG20C	XILINX	获取价格	In-System-Programmable Configuration PROMs
XC18V01PCG20C0901	XILINX	获取价格	Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20
XC18V01SO20	XILINX	获取价格	In-System Programmable Configuration PROMs

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