Datasheet > XC18V01PC20C0936

XC18V01PC20C0936

更新时间： 2024-11-12 10:09:19

品牌	Logo	应用领域
赛灵思 - XILINX		/
页数	文件大小	规格书
30页	607K
描述
Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20

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XC18V01PC20C0936 数据手册

XC18V00 Series In-System

Programmable Configuration

PROMs

DS026 (v3.10) April 17, 2003

Product Specification

•

Dual configuration modes

Features

Serial Slow/Fast configuration (up to 33 MHz)

Parallel (up to 264 Mb/s at 33 MHz)

•

In-system programmable 3.3V PROMs for

configuration of Xilinx FPGAs

Endurance of 20,000 program/erase cycles

•

5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals

3.3V or 2.5V output capability

Program/erase over full commercial/industrial

voltage and temperature range

Available in PC20, SO20, PC44 and VQ44 packages

•

IEEE Std 1149.1 boundary-scan (JTAG) support

Simple interface to the FPGA

Design support using the Xilinx Alliance and

Foundation series software packages.

Cascadable for storing longer or multiple bitstreams

Low-power advanced CMOS FLASH process

•

JTAG command initiation of standard FPGA

configuration

Description

Xilinx introduces the XC18V00 series of in-system program-

mable configuration PROMs (Figure 1). Devices in this 3.3V

family include a 4-megabit, a 2-megabit, a 1-megabit, a

When the FPGA is in Master-SelectMAP mode, the FPGA

generates a configuration clock that drives the PROM.

When the FPGA is in Slave-Parallel or Slave-SelectMAP

Mode, an external oscillator generates the configuration

clock that drives the PROM and the FPGA. After CE and OE

are enabled, data is available on the PROMs DATA (D0-D7)

pins. New data is available a short access time after each

rising clock edge. The data is clocked into the FPGA on the

following rising edge of the CCLK. Neither Slave-Parallel

nor SelectMAP utilize a Length Count, so a free-running

oscillator can be used in the Slave-Parallel or Slave-

SelecMAP modes.

512-Kbit, and

256-Kbit PROM that provide an

easy-to-use, cost-effective method for re-programming and

storing large Xilinx FPGA or CPLD configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after CE and OE are enabled, data is available on the

PROM DATA (D0) pin that is connected to the FPGA D

pin. New data is available a short access time after each ris-

ing clock edge. The FPGA generates the appropriate num-

ber of clock pulses to complete the configuration. When the

FPGA is in Slave Serial mode, the PROM and the FPGA are

clocked by an external clock.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family or with

the XC17V00 one-time programmable Serial PROM family.

other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,

application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may

require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties

or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

DS026 (v3.10) April 17, 2003

www.xilinx.com

Product Specification

1-800-255-7778

12 3 4 5 6 7...30

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与XC18V01PC20C0936相关器件

型号	品牌	获取价格	描述	数据表
XC18V01PC20I	ETC	获取价格	Sequential Access Serial EEPROM
XC18V01PC44	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01PC44C	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01PCG20C	XILINX	获取价格	In-System-Programmable Configuration PROMs
XC18V01PCG20C0901	XILINX	获取价格	Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQCC20, PLASTIC, LCC-20
XC18V01SO20	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01SO20C	XILINX	获取价格	In-System Programmable Configuration PROMs
XC18V01SO20C0901	XILINX	获取价格	Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PDSO20, SOIC-20
XC18V01SO20I	ETC	获取价格	Sequential Access Serial EEPROM
XC18V01SOG20C	XILINX	获取价格	In-System-Programmable Configuration PROMs

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