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XA2C64A-7VQG100I PDF预览

XA2C64A-7VQG100I

更新时间： 2024-09-19 20:09:43
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
14页 217K
描述
Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, VQFP-100

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XA2C64A-7VQG100I 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TFQFP, TQFP44,.47SQ,32针数：100
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.28其他特性：REAL DIGITAL DESIGN TECHNOLOGY
系统内可编程：YESJESD-30 代码：S-PQFP-G100
JESD-609代码：e3JTAG BST：YES
长度：14 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：64
宏单元数：64端子数量：100
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 64 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装等效代码：TQFP44,.47SQ,32封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：7.5 ns认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.2 mm
子类别：Programmable Logic Devices最大供电电压：1.9 V
最小供电电压：1.7 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

XA2C64A-7VQG100I 数据手册

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0
R
CoolRunner-II Automotive CPLD  
Product Family  
0
0
DS315 (v1.1) October 31, 2006  
Product Specification  
-
-
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pullup on select  
I/O pins  
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels on all parts  
Hot pluggable  
Features  
•
AEC-Q100 device qualification and full PPAP support  
available in both I-grade and extended temperature  
Q-grade  
-
-
•
Guaranteed to meet full electrical specifications over  
TA = -40° C to +105° C with TJ Maximum = +125° C  
(Q-grade)  
-
•
•
Optimized for 1.8V systems  
•
•
PLA architecture  
-
-
Industry’s fastest low power CPLD  
Densities from 32 to 384 macrocells  
-
-
Superior pinout retention  
100% product term routability across function block  
Industry’s best 0.18 micron CMOS CPLD  
Wide package availability including fine pitch:  
-
-
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
Guaranteed 1,000 program/erase cycles  
Guaranteed 20 year data retention  
-
-
Chip Scale BGA, TQFP, and VQFP packages  
XA devices use Pb-free packages  
•
•
Design entry/verification using Xilinx and industry  
standard CAE tools  
•
Advanced system features  
-
Free software support for all densities using Xilinx  
WebPACK™  
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
·
WARNING: Programming temperature range of  
TA = 0° C to +70° C  
-
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt trigger input (per pin)  
Multiple I/O banks on all devices  
Family Overview  
Unsurpassed low power management  
Xilinx CoolRunner™-II Automotive CPLDs deliver the high  
speed and ease of use associated with the XA9500XL  
CPLD family, along with extremely low power versatility in a  
single CPLD. This means that the exact same parts can be  
used for high-speed data communications/ computing sys-  
tems and leading edge portable products, with the added  
benefit of In System Programming. Low power consumption  
and high-speed operation are combined into a single family  
that is easy to use and cost effective. Clocking techniques  
and other power saving features extend the users’ power  
budget. The design features are supported with Xilinx ISE  
WebPACK. Additional details can be found in Further  
Reading, page 13.  
·
DataGATE external signal control  
-
Flexible clocking modes  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (÷ 2,4,6,8,10,12,14,16)  
CoolCLOCK  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
Multiple global output enables  
Global set/reset  
·
·
-
-
Abundant product term clocks, output enables and  
set/resets  
Efficient control term clocks, output enables and  
set/resets for each macrocell and shared across  
function blocks  
Table 1 shows the macrocell capacity and key timing  
parameters for the CoolRunner-II Automotive CPLD family.  
-
Advanced design security  
Table 1: CoolRunner-II Automotive CPLD Family Parameters  
XA2C32A  
32  
XA2C64A  
64  
XA2C128  
128  
XA2C256  
256  
XA2C384  
384  
Macrocells  
Max I/O  
33  
64  
100  
118  
118  
T
T
T
F
PD (ns)  
5.5  
6.7  
7.0  
7.0  
9.2  
SU (ns)  
2.6  
2.5  
3.0  
2.8  
3.3  
CO (ns)  
4.7  
6.0  
5.4  
6.0  
7.9  
SYSTEM1 (MHz)  
200  
159  
152  
152  
125  
© 2004-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS315 (v1.1) October 31, 2006  
www.xilinx.com  
1
Product Specification  
1234567...14

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XA2C64A-7VQG100I 替代型号

型号 品牌 替代类型 描述 数据表
XC2C64A-7VQG44C XILINX

类似代替

 Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
XC2C64A-5VQG44C XILINX

类似代替

 Flash PLD, 5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44

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XA2C64A-8VQG44Q XILINX

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XA2S300E-6FT256I XILINX

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XA2S300E-6FT256Q XILINX

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