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XA2C64A-8VQG44Q PDF预览

XA2C64A-8VQG44Q

更新时间： 2024-09-19 20:00:31
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
16页 417K
描述
Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, VQFP-44

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XA2C64A-8VQG44Q 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TQFP, TQFP44,.47SQ,32针数：44
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：1.6其他特性：REAL DIGITAL DESIGN TECHNOLOGY
系统内可编程：YESJESD-30 代码：S-PQFP-G44
JESD-609代码：e3JTAG BST：YES
长度：10 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：33
宏单元数：64端子数量：44
最高工作温度：125 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 33 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装等效代码：TQFP44,.47SQ,32封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：7.5 ns认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.2 mm
子类别：Programmable Logic Devices最大供电电压：1.9 V
最小供电电压：1.7 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：10 mmBase Number Matches：1

XA2C64A-8VQG44Q 数据手册

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XA2C64A CoolRunner-II  
Automotive CPLD  
0
0
DS553 (v1.1) May 5, 2007  
Product Specification  
Refer to the CoolRunner™-II Automotive CPLD family data  
sheet for architecture description.  
Features  
•
AEC-Q100 device qualification and full PPAP support  
available in both I-grade and extended temperature  
Q-grade  
WARNING: Programming temperature range of  
TA = 0° C to +70° C.  
•
Guaranteed to meet full electrical specifications over  
TA = -40° C to +105° C with TJ Maximum = +125° C  
Description  
(Q-grade)  
The CoolRunner-II Automotive 64-macrocell device is  
designed for both high performance and low power applica-  
tions. This lends power savings to high-end communication  
equipment and high speed to battery operated devices. Due  
to the low power stand-by and dynamic operation, overall  
system reliability is improved  
•
•
Optimized for 1.8V systems  
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
•
•
Available in the following package options  
This device consists of four Function Blocks inter-con-  
nected by a low power Advanced Interconnect Matrix (AIM).  
The AIM feeds 40 true and complement inputs to each  
Function Block. The Function Blocks consist of a 40 by 56  
P-term PLA and 16 macrocells which contain numerous  
configuration bits that allow for combinational or registered  
modes of operation.  
-
-
-
44-pin VQFP with 33 user I/O  
100-pin VQFP with 64 user I/O  
Pb-free only for all packages  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
·
-
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Two separate I/O banks  
RealDigital™ 100% CMOS product term  
generation  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as "direct input" registers to store signals directly  
from input pins.  
-
-
Flexible clocking modes  
·
Optional DualEDGE triggered registers  
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
·
·
Multiple global output enables  
Global set/reset  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
-
Efficient control term clocks, output enables and  
set/resets for each macrocell and shared across  
function blocks  
Advanced design security  
Optional bus-hold, 3-state or weak pullup on  
selected I/O pins  
Open-drain output option for Wired-OR and LED  
drive  
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
-
-
-
-
-
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
-
PLA architecture  
·
·
Superior pinout retention  
100% product term routability across function  
block  
The CoolRunner-II Automotive 64-macrocell CPLD is I/O  
compatible with standard LVTTL and LVCMOS18,  
LVCMOS25, and LVCMOS33 (see Table 1). This device is  
-
Hot pluggable  
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS553 (v1.1) May 5, 2007  
www.xilinx.com  
1
Product Specification  
1234567...16

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XA2C64A-8VQG44Q 替代型号

型号 品牌 替代类型 描述 数据表
XC2C64A-7VQG44C XILINX

完全替代

 Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
XC2C64A-5VQG44C XILINX

完全替代

 Flash PLD, 5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44

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