5秒后页面跳转
捷配首页

Datasheet > XA2S300E-6FT256Q
XA2S300E-6FT256Q PDF预览

XA2S300E-6FT256Q

更新时间： 2024-09-19 20:00:43
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
6页 125K
描述
Field Programmable Gate Array, 1536 CLBs, 357MHz, 6912-Cell, CMOS, PBGA256, FBGA-256

阅读下载

中文翻译

获取价格

XA2S300E-6FT256Q 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：FBGA-256针数：256
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.83
最大时钟频率：357 MHzJESD-30 代码：S-PBGA-B256
JESD-609代码：e0湿度敏感等级：3
可配置逻辑块数量：1536输入次数：182
逻辑单元数量：6912输出次数：182
端子数量：256最高工作温度：125 °C
最低工作温度：-40 °C组织：1536 CLBS
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA256,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：240
电源：1.2/3.6,1.8 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified筛选级别：AEC-Q100
子类别：Field Programmable Gate Arrays最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
Base Number Matches：1

XA2S300E-6FT256Q 数据手册

 浏览型号XA2S300E-6FT256Q的Datasheet PDF文件第2页浏览型号XA2S300E-6FT256Q的Datasheet PDF文件第3页浏览型号XA2S300E-6FT256Q的Datasheet PDF文件第4页浏览型号XA2S300E-6FT256Q的Datasheet PDF文件第5页浏览型号XA2S300E-6FT256Q的Datasheet PDF文件第6页 
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —  
0
Spartan-IIE 1.8V FPGA  
R
Automotive XA Product Family:  
Introduction and Ordering  
0
0
DS106-1 (v2.0) August 9, 2013  
Product Specification  
•
•
Guaranteed to meet full electrical specifications over  
Introduction  
T = –40°C to +125°C  
J
The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Pro-  
grammable Gate Array family is specifically designed to  
meet the needs of high-volume, cost-sensitive automotive  
electronic applications. The family gives users high perfor-  
mance, abundant logic resources, and a rich feature set, all  
at an exceptionally low price. The five-member family offers  
densities ranging from 50,000 to 300,000 system gates, as  
shown in Table 1. System performance is supported beyond  
200 MHz.  
Second generation ASIC replacement technology  
-
Densities as high as 6,912 logic cells with up to  
300,000 system gates  
-
Very low cost  
•
System-level features  
-
SelectRAM+™ hierarchical memory:  
·
·
·
16 bits/LUT distributed RAM  
Configurable 4K-bit true dual-port block RAM  
Fast interfaces to external RAM  
Spartan-IIE devices deliver more gates, I/Os, and features  
per dollar than other FPGAs by combining advanced pro-  
cess technology with a streamlined architecture based on  
the proven Virtex™-E platform. Features include block RAM  
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable  
I/O standards, and four DLLs (Delay-Locked Loops). Fast,  
predictable interconnect means that successive design iter-  
ations continue to meet timing requirements.  
-
-
-
-
-
Dedicated carry logic for high-speed arithmetic  
Efficient multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with enable, set, reset  
Four dedicated DLLs for advanced clock control  
·
Eliminate clock distribution delay  
·
Multiply, divide, or phase shift  
-
-
Four primary low-skew global clock distribution nets  
IEEE 1149.1 compatible boundary scan logic  
XA devices are available in both the extended-temperature  
Q-grade (-40°C to +125°C) and industrial I-grade (-40°C to  
+100°C) and are qualified to the industry-recognized  
AEC-Q100 standard.  
•
•
Versatile I/O and packaging  
-
-
Low-cost packages available in all densities  
19 high-performance interface standards  
The XA Spartan-IIE family is a superior alternative to  
mask-programmed ASICs. The FPGA avoids the initial cost,  
lengthy development cycles, and inherent risk of conven-  
tional ASICs. Also, FPGA programmability permits design  
upgrades in the field with no hardware replacement neces-  
sary (impossible with ASICs).  
·
·
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL  
LVDS and LVPECL differential I/O  
-
Up to 120 differential I/O pairs that can be input,  
output, or bidirectional  
Fully supported by powerful Xilinx ISE development  
system  
-
-
-
Fully automatic mapping, placement, and routing  
Integrated with design entry and verification tools  
Extensive IP library including DSP functions  
Features  
•
AEC-Q100 device qualification and full PPAP support  
available in both extended temperature Q-grade and  
I-grade  
Table 1: XA Spartan-IIE FPGA Family Members  
Typical  
CLB  
Maximum  
Maximum  
Logic System Gate Range  
Array  
Total  
Available Differential Distributed  
Block  
RAM Bits  
(1)  
Device  
XA2S50E  
XA2S100E  
XA2S150E  
XA2S200E  
XA2S300E  
Notes:  
Cells  
1,728  
2,700  
3,888  
5,292  
6,912  
(Logic and RAM)  
23,000 - 50,000  
37,000 - 100,000  
52,000 - 150,000  
71,000 - 200,000  
93,000 - 300,000  
(R x C) CLBs User I/O  
I/O Pairs  
RAM Bits  
24,576  
38,400  
55,296  
75,264  
98,304  
16 x 24  
20 x 30  
24 x 36  
384  
600  
864  
102  
102  
182  
182  
182  
83  
32K  
40K  
48K  
56K  
64K  
86  
114  
28 x 42 1,176  
32 x 48 1,536  
120  
120  
1. User I/O counts include the four global clock/user input pins. See details in Table 3, page 5  
© 2002–2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS106-1 (v2.0) August 9, 2013  
www.xilinx.com  
1
Product Specification  
123456

中文翻译

下载PDF

XA2S300E-6FT256Q 替代型号

型号 品牌 替代类型 描述 数据表
XA2S300E-6FT256I XILINX

完全替代

 Field Programmable Gate Array, 1536 CLBs, 357MHz, 6912-Cell, CMOS, PBGA256, FBGA-256

与XA2S300E-6FT256Q相关器件

型号 品牌 获取价格 描述 数据表
XA2S50E-6TQ144I XILINX

获取价格

 		Field Programmable Gate Array, 384 CLBs, 357MHz, 1728-Cell, CMOS, PQFP144, PLASTIC, TQFP-1
XA2S50E-6TQ144Q XILINX

获取价格

 		Field Programmable Gate Array, 384 CLBs, 357MHz, 1728-Cell, CMOS, PQFP144, PLASTIC, TQFP-1
XA3S1000-4FG456I XILINX

获取价格

 		Field Programmable Gate Array, 1920 CLBs, 1000000 Gates, 125MHz, 17280-Cell, PBGA456, FBGA
XA3S1000-4FG456Q XILINX

获取价格

 		Field Programmable Gate Array, 1920 CLBs, 1000000 Gates, 125MHz, 17280-Cell, PBGA456, FBGA
XA3S1000-4FGG456I XILINX

获取价格

 		Field Programmable Gate Array, 1920 CLBs, 1000000 Gates, 125MHz, 17280-Cell, PBGA456, LEAD
XA3S1000-4FGG456Q XILINX

获取价格

 		Field Programmable Gate Array, 1920 CLBs, 1000000 Gates, 125MHz, 17280-Cell, PBGA456, LEAD
XA3S1000-4FT256I XILINX

获取价格

 		Field Programmable Gate Array, 125MHz, 17280-Cell, PQFP100,
XA3S1000-4FT256Q XILINX

获取价格

 		Field Programmable Gate Array, 125MHz, 17280-Cell, PQFP100,
XA3S1000-4FTG256Q XILINX

获取价格

 		Field Programmable Gate Array, 1920 CLBs, 1000000 Gates, 125MHz, 17280-Cell, PBGA256, LEAD
XA3S100E-4CPG132I XILINX

获取价格

 		Field Programmable Gate Array, 240 CLBs, 100000 Gates, 572MHz, 2160-Cell, CMOS, PBGA132, L

与XA2S300E-6FT256Q相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证