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XA2S100E-6TQ144Q PDF预览

XA2S100E-6TQ144Q

更新时间： 2024-11-08 19:56:47
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
6页 82K
描述
Field Programmable Gate Array, 600 CLBs, 357MHz, 2700-Cell, CMOS, PQFP144, PLASTIC, TQFP-144

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XA2S100E-6TQ144Q 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, TQFP-144针数：144
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.83
最大时钟频率：357 MHzJESD-30 代码：S-PQFP-G144
JESD-609代码：e0湿度敏感等级：3
可配置逻辑块数量：600输入次数：102
逻辑单元数量：2700输出次数：102
端子数量：144最高工作温度：125 °C
最低工作温度：-40 °C组织：600 CLBS
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：225
电源：1.2/3.6,1.8 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified筛选级别：AEC-Q100
子类别：Field Programmable Gate Arrays最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
Base Number Matches：1

XA2S100E-6TQ144Q 数据手册

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —  
0
Spartan-IIE 1.8V FPGA  
R
Automotive XA Product Family:  
Introduction and Ordering  
0
0
DS106-1 (v2.0) August 9, 2013  
Product Specification  
•
•
Guaranteed to meet full electrical specifications over  
Introduction  
T = –40°C to +125°C  
J
The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Pro-  
grammable Gate Array family is specifically designed to  
meet the needs of high-volume, cost-sensitive automotive  
electronic applications. The family gives users high perfor-  
mance, abundant logic resources, and a rich feature set, all  
at an exceptionally low price. The five-member family offers  
densities ranging from 50,000 to 300,000 system gates, as  
shown in Table 1. System performance is supported beyond  
200 MHz.  
Second generation ASIC replacement technology  
-
Densities as high as 6,912 logic cells with up to  
300,000 system gates  
-
Very low cost  
•
System-level features  
-
SelectRAM+™ hierarchical memory:  
·
·
·
16 bits/LUT distributed RAM  
Configurable 4K-bit true dual-port block RAM  
Fast interfaces to external RAM  
Spartan-IIE devices deliver more gates, I/Os, and features  
per dollar than other FPGAs by combining advanced pro-  
cess technology with a streamlined architecture based on  
the proven Virtex™-E platform. Features include block RAM  
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable  
I/O standards, and four DLLs (Delay-Locked Loops). Fast,  
predictable interconnect means that successive design iter-  
ations continue to meet timing requirements.  
-
-
-
-
-
Dedicated carry logic for high-speed arithmetic  
Efficient multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with enable, set, reset  
Four dedicated DLLs for advanced clock control  
·
Eliminate clock distribution delay  
·
Multiply, divide, or phase shift  
-
-
Four primary low-skew global clock distribution nets  
IEEE 1149.1 compatible boundary scan logic  
XA devices are available in both the extended-temperature  
Q-grade (-40°C to +125°C) and industrial I-grade (-40°C to  
+100°C) and are qualified to the industry-recognized  
AEC-Q100 standard.  
•
•
Versatile I/O and packaging  
-
-
Low-cost packages available in all densities  
19 high-performance interface standards  
The XA Spartan-IIE family is a superior alternative to  
mask-programmed ASICs. The FPGA avoids the initial cost,  
lengthy development cycles, and inherent risk of conven-  
tional ASICs. Also, FPGA programmability permits design  
upgrades in the field with no hardware replacement neces-  
sary (impossible with ASICs).  
·
·
LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL  
LVDS and LVPECL differential I/O  
-
Up to 120 differential I/O pairs that can be input,  
output, or bidirectional  
Fully supported by powerful Xilinx ISE development  
system  
-
-
-
Fully automatic mapping, placement, and routing  
Integrated with design entry and verification tools  
Extensive IP library including DSP functions  
Features  
•
AEC-Q100 device qualification and full PPAP support  
available in both extended temperature Q-grade and  
I-grade  
Table 1: XA Spartan-IIE FPGA Family Members  
Typical  
CLB  
Maximum  
Maximum  
Logic System Gate Range  
Array  
Total  
Available Differential Distributed  
Block  
RAM Bits  
(1)  
Device  
XA2S50E  
XA2S100E  
XA2S150E  
XA2S200E  
XA2S300E  
Notes:  
Cells  
1,728  
2,700  
3,888  
5,292  
6,912  
(Logic and RAM)  
23,000 - 50,000  
37,000 - 100,000  
52,000 - 150,000  
71,000 - 200,000  
93,000 - 300,000  
(R x C) CLBs User I/O  
I/O Pairs  
RAM Bits  
24,576  
38,400  
55,296  
75,264  
98,304  
16 x 24  
20 x 30  
24 x 36  
384  
600  
864  
102  
102  
182  
182  
182  
83  
32K  
40K  
48K  
56K  
64K  
86  
114  
28 x 42 1,176  
32 x 48 1,536  
120  
120  
1. User I/O counts include the four global clock/user input pins. See details in Table 3, page 5  
© 2002–2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS106-1 (v2.0) August 9, 2013  
www.xilinx.com  
1
Product Specification  
 
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XA3S1000-4FG456I XILINX

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XA3S1000-4FG456Q XILINX

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