Datasheet > X2N4119A

X2N4119A

更新时间： 2024-09-14 23:29:59

品牌	Logo	应用领域
其他 - ETC		晶体晶体管
页数	文件大小	规格书
1页	22K
描述
TRANSISTOR \| JFET \| N-CHANNEL \| 200UA I(DSS) \| CHIP

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X2N4119A 数据手册

N-Channel JFET

General Purpose Amplifier

CORPORATION

2N4117 – 2N4119 / 2N4117A – 2N4119A

PN4117 – PN4119 / PN4117A – PN4119A / SST4117 – SST4119

FEATURES

PIN CONFIGURATION

Low Leakage

•

Low Capacitance

•

ABSOLUTE MAXIMUM RATINGS

(T_A= 25^oC unless otherwise noted)

TO-92

TO-72

Gate-Source or Gate-Drain Voltage . . . . . . . . . . . . . . . . -40V

Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Storage Temperature Range . . . . . . . . . . . . . -65^oC to +200^oC

Operating Temperature Range . . . . . . . . . . . -55^oC to +175^oC

Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300^oC

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mW

Derate above 25^oC . . . . . . . . . . . . . . . . . . . . . . . 2.0mW/^oC

SOT-23

NOTE: Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. These are

stress ratings only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

5007

ORDERING INFORMATION

PRODUCT MARKING (SOT-23)

Part

Package

Temperature Range

SST4117

SST4118

SST4119

T17

T18

T19

2N4117-19/A Hermetic TO-72

PN4117-19/A Plastic TO-92

SST4117-19 Plastic SOT-23

-55^oC to +175^oC

-55^oC to +135^oC

X2N4117-19/A Sorted Chips in Carriers -55^oC to +175^oC

ELECTRICAL CHARACTERISTICS (T_A= 25^oC unless otherwise specified)

4117/A

4118/A

4119/A

SYMBOL

PARAMETER

UNITS

TEST CONDITIONS

MIN MAX MIN MAX MIN MAX

-40 -40 -40

BV_GSS

Gate-Source Breakdown Voltage

Gate Reverse Current

I_G= -1µA, V_DS= 0

-10

-1

-10

-1

-10

-1

A devices

V_GS= -20V, V_DS= 0

T_A= +150^oC

I_GSS

-25

-2.5

-25

-2.5

-3

-25

-2.5

-6

V_GS(off)

I_DSS

g_fs

Gate-Source Pinch-Off Voltage

-0.6 -1.8

-1

-2

V_DS= 10V, I_D= 1nA

V_DS= 10V, V_GS= 0

0.02 0.09 0.08 0.24 0.20 0.60 mA

70 210 80 250 100 330

Drain Current at Zero Gate Voltage (Note 1)

Common-Source Forward Transconductance (Note 1)

Common-Source Forward Transconductance (Note 2)

Common-Source Output Conductance

V_DS= 10V, f = 1kHz

V_GS= 0, f = 30MHz

V_DS= 10V, V_GS= 0, f = 1kHz

µS

g_fs

g_os

_DS= 10V, V_GS= 0,

f = 1MHz

C_iss

C_rss

Common-Source Input Capacitance (Note 2)

_DS= 10V, V_GS= 0,

f = 1MHz

1.5

Common-Source Reverse Transfer Capacitance (Note 2)

NOTES: 1. Pulse test: Pulse duration of 2ms used during test.

2. For design reference only, not 100% tested.

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