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VT6508 PDF预览

VT6508

更新时间: 2024-01-14 03:11:45
品牌 Logo 应用领域
其他 - ETC 外围集成电路数据传输控制器局域网以太网局域网(LAN)标准以太网:16GBASE-T时钟
页数 文件大小 规格书
48页 399K
描述
8 RMII PORTS OF 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER

VT6508 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:128
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.92Is Samacsys:N
边界扫描:NO最大时钟频率:50 MHz
最大数据传输速率:12.5 MBpsJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
低功率模式:NO串行 I/O 数:8
端子数量:128最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装形状:RECTANGULAR
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:3.4 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

VT6508 数据手册

 浏览型号VT6508的Datasheet PDF文件第3页浏览型号VT6508的Datasheet PDF文件第4页浏览型号VT6508的Datasheet PDF文件第5页浏览型号VT6508的Datasheet PDF文件第7页浏览型号VT6508的Datasheet PDF文件第8页浏览型号VT6508的Datasheet PDF文件第9页 
VIA Technologies, Inc.  
Preliminary VT6508 Datasheet  
FEATURES  
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Single chip 8 ports 10/100Mbps Ethernet switch controller  
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Highly integrated single chip shared memory switch engine  
Supports 8 RMII (Reduced Media Independent Interface) ports  
Non-blocking layer 2 switch, 148,810 packets/sec on each 100Mbps Ethernet port  
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Media Access Control (MAC)  
Dual 64-byte FIFO’ s per port for receiving and transmitting  
Auto-sensing 10/100Mbps media speed, full/half -duplex mode, and flow-control  
capability  
Two switching mechanisms  
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Supports ‘ store and forward’ switching with filtering CRC-bad packets  
Supports ‘ cut through’ switching subject to long packets of length over 64 bytes  
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Packet buffering  
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Glueless 32-bit interface to SSRAM as a packet buffer pool  
64 packet buffers for 32Kx32 SSRAM, 149 packet buffers for 64Kx32 SSRAM  
1536 bytes for each packet buffer  
Storing control data (forwarding table and packet link entries) in external SSRAM  
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Buffer status is stored in the internal free-buffer bit map registers  
Shared forwarding table of 2K entries (or 4K slots) to support multiple (up to 4K)  
Mac addresses per port  
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Efficient address recognition, self learning, and auto-aging mechanism  
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Two-slot hashing algorithm to prevent hash collision  
Two optional hashing algorithms, CRC-map and direct-map  
Advanced congestion control mechanism  
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IEEE 802.3X compliant flow control for full duplex ports  
Backpressure for half duplex ports  
Drop control for full duplex ports without flow control capability  
Incorporating with the output private buffering scheme to prevent HOL (head of line)  
blocking  
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Supports port mirroring (Sniffer feature)  
By-pass VLAN packets  
Support port-based trunking  
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Support two individual trunk groups, each of 2 member ports  
Load balance according to DMAC address and source port number  
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Support chip initialization through EEPROM or by strapping only  
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Supports I2C EEPROM interface for customized configuration  
Supports LED serial-out in the strapping-only initialization mode  
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50MHz internal reference clock rate  
83~100MHz SSRAM clock rate, typically 83MHz  
Single +3.3V supply, 0.3mm TSMC CMOS technology  
128-pin PQFP package  
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