Standard Products
UT8Q512E 512K x 8 RadTol SRAM
Data Sheet
November 11, 2008
FEATURES
INTRODUCTION
The UT8Q512E RadTol product is a high-performance CMOS
static RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E), an
active LOW Output Enable (G), and three-state drivers.
20ns maximum (3.3 volt supply) address access time
Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Writing to the device is accomplished by taking Chip Enable (E)
and Write Enable (W) inputs LOW. Data on the eight I/O pins
Operational environment:
- Total dose: 50 krads(Si)
(DQ through DQ ) is then written into the location specified
0
7
on the address pins (A through A ). Reading from the device
0
18
2
- SEL Immune 110 MeV-cm /mg
is accomplished by taking Chip Enable (E) and Output Enable
(G) LOW while forcing Write Enable (W) HIGH. Under these
conditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
2
- SEU LET (0.25) = 52 cm MeV
TH
2
- Saturated Cross Section 2.8E-8 cm /bit
-<1.1E-9 errors/bit-day, Adams 90% worst case
environment geosynchronous orbit
The eight input/output pins (DQ through DQ ) are placed in a
0
7
high impedance state when the device is deselected (E HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOW and W LOW).
Packaging:
- 36-lead ceramic flatpack (3.831 grams)
Standard Microcircuit Drawing 5962-99607
- QML Q and V compliant part
Clk. Gen.
Pre-Charge Circuit
A0
A1
A2
Memory Array
1024 Rows
512x8 Columns
A3
A4
A5
A6
A7
A8
I/O Circuit
Column Select
A9
Data
Control
DQ 0 - DQ 7
CLK
Gen.
E
W
G
Figure 1. UT8Q512E SRAM Block Diagram
1