Datasheet > UT8R128K3215WWX

UT8R128K3215WWX

更新时间： 2024-09-14 00:54:03

品牌	Logo	应用领域
艾法斯 - AEROFLEX		静态存储器
页数	文件大小	规格书
22页	274K
描述
UT8R128K32 128K x 32 SRAM

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UT8R128K3215WWX 数据手册

Standard Products

UT8R128K32 128K x 32 SRAM

Data Sheet

March 2009

www.aeroflex.com/memories

FEATURES

INTRODUCTION

15ns maximum access time

The UT8R128K32 is a high-performance CMOS static RAM

organized as 131,072 words by 32 bits. Easy memory expansion

is provided by active LOW and HIGH chip enables (E1, E2), an

active LOW output enable (G), and three-state drivers. This

device has a power-down feature that reduces power

Asynchronous operation, functionally compatible with

industry-standard 128K x 32 SRAMs

CMOS compatible inputs and output levels, three-state

bidirectional data bus

- I/O Voltage 3.3 volts, 1.8 volt core

Operational environment:

consumption by more than 90% when deselected.

Writing to the device is accomplished by taking chip enable one

(E1) input LOW, chip enable two (E2) HIGH and write enable

(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)

is then written into the location specified on the address pins

(A0 through A16). Reading from the device is accomplished by

taking chip enable one (E1) and output enable (G) LOW while

forcing write enable(W) and chip enable two(E2) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins will appear on the I/O pins.

- Total-dose: 300 Krad(Si)

- SEL Immune: >100 MeV-cm /mg

- LET (0.25): 53.0 MeV-cm /mg

- Memory Cell Saturated Cross Section: 1.67E-7cm /bit

- Neutron Fluence: 3.0E14n/cm

- Dose Rate

- Upset 1.0E9 rad(Si)/sec

- Latchup >1.0E11 rad(Si)/sec

Packaging options:

The 32 input/output pins (DQ0 through DQ31) are placed in a

high impedance state when the device is deselected (E1 HIGH

or E2 LOW), the outputs are disabled (G HIGH), or during a

write operation (E1 LOW, E2 HIGH and W LOW).

- 68-lead ceramic quad flatpack (6.19 grams)

Standard Microcircuit Drawing 5962-03236

- QML Q & V compliant part

Pre-Charge Circuit

Memory Array

256K x 16

HHWE

LHWE

I/O Circuit

Column Select

•

Low Word

Read Circuit

DQ(15) to DQ(0)

DQ(31) to DQ(16)

Data Control

•

Data Control

A10 A11 A12 A13A14 A15 A16

High Word

Read Circuit

Figure 1. UT8R128K32 SRAM Block Diagram

12 3 4 5 6 7...22

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