Datasheet > UT8R512K8

UT8R512K8

更新时间： 2024-10-31 00:54:03

品牌	Logo	应用领域
艾法斯 - AEROFLEX		静态存储器
页数	文件大小	规格书
23页	236K
描述
UT8R512K8 512K x 8 SRAM

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中文翻译

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数据手册

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UT8R512K8 数据手册

Standard Products

UT8R512K8 512K x 8 SRAM

Data Sheet

March 2009

www.aeroflex.com/memories

FEATURES

INTRODUCTION

15ns maximum access time

Asynchronous operation for compatibility with industry-

standard 512K x 8 SRAMs

The UT8R512K8 is a high-performance CMOS static RAM

organized as 524,288 words by 8 bits. Easy memory expansion

is provided by active LOW and HIGH chip enables (E1, E2), an

active LOW output enable (G), and three-state drivers. This

device has a power-down feature that reduces power

consumption by more than 90% when deselected.

CMOS compatible inputs and output levels, three-state

bidirectional data bus

- I/O Voltage 3.3 volts, 1.8 volt core

Operational environment:

- Intrinsic total-dose: 300K rad(Si)

Writing to the device is accomplished by taking chip enable one

(E1) input LOW, chip enable two (E2) HIGH and write enable

(W) input LOW. Data on the eight I/O pins (DQ0 through DQ7)

is then written into the location specified on the address pins

(A0 through A18). Reading from the device is accomplished by

taking chip enable one (E1) and output enable (G) LOW while

forcing write enable(W) and chip enable two(E2) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins will appear on the I/O pins.

- SEL Immune >100 MeV-cm /mg

- LET (0.25): 53.0 MeV-cm /mg

- Memory Cell Saturated Cross Section 1.67E-7cm /bit

- Neutron Fluence: 3.0E14n/cm

- Dose Rate

- Upset 1.0E9 rad(Si)/sec

- Latchup >1.0E11 rad(Si)/sec

Packaging options:

- 36-lead ceramic flatpack (3.762 grams)

Standard Microcircuit Drawing 5962-03235

- QML Q & Vcompliant part

The eight input/output pins (DQ0 through DQ7) are placed in a

high impedance state when the device is deselected (E1 HIGH

or E2 LOW), the outputs are disabled (G HIGH), or during a

write operation (E1 LOW, E2 HIGH and W LOW).

INPUT

DRIVER

TOP/BOTTOM

DECODER

INPUT

DRIVERS

BLOCK

DECODER

A(18:0)

ROW

DECODER

MEMORY

ARRAY

INPUT

DRIVERS

DATA

WRITE

CIRCUIT

INPUT

DRIVERS

INPUT

DRIVERS

COLUMN

DECODER

COLUMN

I/O

DQ(7:0)

OUTPUT

DRIVERS

DATA

READ

CIRCUIT

CHIP ENABLE

OUTPUT ENABLE

WRITE ENABLE

Figure 1. UT8R512K8 SRAM Block Diagram

12 3 4 5 6 7...23

中文翻译

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