Datasheet > UT8Q512K32E

UT8Q512K32E

更新时间： 2024-10-31 01:12:23

品牌	Logo	应用领域
艾法斯 - AEROFLEX		静态存储器
页数	文件大小	规格书
21页	226K
描述
UT8Q512K32E 16 Megabit RadTolerant SRAM MCM

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UT8Q512K32E 数据手册

Standard Products

UT8Q512K32E 16 Megabit RadTolerant SRAM MCM

Data Sheet

June 28, 2011

FEATURES

INTRODUCTION

TheUT8Q512K32ERadTolerantproductisahigh-performance



25ns maximum (3.3 volt supply) address access time

2M byte (16Mbit) CMOS static RAM multi-chip module

(MCM), organized as four individual 524,288 x 8 bit SRAMs

with a common output enable. Memory expansion is provided

by an active LOW chip enable (En), an active LOW output

enable (G), and three-state drivers. This device has a power-

downfeaturethatreducespowerconsumptionbymorethan90%

when deselected.

MCM contains four (4) 512Kx8 industry-standard

asynchronous SRAMs; the control architecture allows

operation as 8, 16, 24 or 32-bit data width



TTL compatible inputs and output levels, three-state

bidirectional data bus

Typical radiation performance

- Total dose: 50krads

- SEL Immune >110 MeV-cm /mg

Writing to each memory is accomplished by taking chip enable

(En) input LOW and write enable (Wn) inputs LOW. Data on

the eight I/O pins (DQ through DQ ) is then written into the

- SEU LET (0.25) = >52 MeV-cm /mg

- Saturated Cross Section , 2.8E-8 cm /bit

- <1.1E-9 errors/bit-day, Adams 90% geosynchronous

heavy ion

locationspecifiedontheaddresspins(A throughA ). Reading

from the device is accomplished by taking chip enable (En) and

output enable (G) LOW while forcing write enable (Wn) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins will appear on the I/O pins.



Packaging:

- 68-lead dual cavity ceramic quad flatpack (CQFP)

(11.0 grams)

The input/output pins are placed in a high impedance state when

the device is deselected (En HIGH), the outputs are disabled (G

HIGH), or during a write operation (En LOW and Wn LOW).

Perform 8, 16, 24 or 32 bit accesses by making Wn along with

En a common input to any combination of the discrete memory

die.

Standard Microcircuit Drawing 5962-01533

- QML Q and Vcompliant part

A(18:0)

512K x 8

DQ(23:16)

DQ2(7:0)

DQ(15:8)

DQ1(7:0)

DQ(31:24)

DQ3(7:0)

DQ(7:0)

DQ0(7:0)

Figure 1. UT8Q512K32E SRAM Block Diagram

12 3 4 5 6 7...21

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与UT8Q512K32E相关器件

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