5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> UPD4482162GF-C60
UPD4482162GF-C60 PDF预览

UPD4482162GF-C60

更新时间： 2024-11-17 22:59:31
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路静态存储器
页数 文件大小 规格书
28页 441K
描述
8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT

阅读下载

中文翻译

获取价格

UPD4482162GF-C60 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：14 X 20 MM, PLASTIC, LQFP-100Reach Compliance Code：compliant
风险等级：5.92最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：8388608 bit内存集成电路类型：CACHE SRAM
内存宽度：16功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX16封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

UPD4482162GF-C60 数据手册

 浏览型号UPD4482162GF-C60的Datasheet PDF文件第2页浏览型号UPD4482162GF-C60的Datasheet PDF文件第3页浏览型号UPD4482162GF-C60的Datasheet PDF文件第4页浏览型号UPD4482162GF-C60的Datasheet PDF文件第5页浏览型号UPD4482162GF-C60的Datasheet PDF文件第6页浏览型号UPD4482162GF-C60的Datasheet PDF文件第7页 
DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD4482162, 4482182, 4482322, 4482362  
8M-BIT CMOS SYNCHRONOUS FAST SRAM  
PIPELINED OPERATION  
SINGLE CYCLE DESELECT  
Description  
The µPD4482162 is a 524,288-word by 16-bit, the µPD4482182 is a 524,288-word by 18-bit, µPD4482322 is a 262,144-  
word by 32-bit and the µPD4482362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS  
technology using Full-CMOS six-transistor memory cell.  
The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 integrates unique synchronous peripheral circuitry, 2-  
bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single  
clock input (CLK).  
The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 are suitable for applications which require synchronous  
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In  
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.  
The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 are packaged in 100-pin PLASTIC LQFP with a 1.4  
mm package thickness for high density and low capacitive loading.  
Features  
• 3.3 V or 2.5 V core supply  
• Synchronous operation  
• Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -C60)  
TA = −40 to +85 °C (-A44Y, -A50Y, -A60Y, -C60Y)  
• Internally self-timed write control  
• Burst read / write : Interleaved burst and linear burst sequence  
• Fully registered inputs and outputs for pipelined operation  
• Single-Cycle deselect timing  
• All registers triggered off positive clock edge  
• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs  
• Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)  
• Asynchronous output enable : /G  
• Burst sequence selectable : MODE  
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
• Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482322, µPD4482362)  
/BW1, /BW2, /BWE (µPD4482162, µPD4482182)  
Global write enable : /GW  
• Three chip enables for easy depth expansion  
• Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M14522EJ3V0DS00 (3rd edition)  
Date Published December 2002 NS CP(K)  
Printed in Japan  
The mark  shows major revised points.  
2000  
1234567...28

中文翻译

下载PDF

与UPD4482162GF-C60相关器件

型号 品牌 获取价格 描述 数据表
UPD4482162GF-C60-A NEC

获取价格

 		暂无描述
UPD4482162GF-C60Y NEC

获取价格

 		8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT
UPD4482162GF-C60Y-A NEC

获取价格

 		暂无描述
UPD4482163 NEC

获取价格

 		8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT
UPD4482163GF-A44 NEC

获取价格

 		8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT
UPD4482163GF-A44 RENESAS

获取价格

 		暂无描述
UPD4482163GF-A44-A NEC

获取价格

 		Cache SRAM, 512KX16, 2.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD4482163GF-A44Y NEC

获取价格

 		8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT
UPD4482163GF-A44Y RENESAS

获取价格

 		Cache SRAM, 512KX16, 2.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD4482163GF-A44Y-A RENESAS

获取价格

 		IC,SYNC SRAM,512KX16,CMOS,QFP,100PIN,PLASTIC

与UPD4482162GF-C60相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证