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UPD4482181GF-A75Y PDF预览

UPD4482181GF-A75Y

更新时间: 2024-11-01 13:15:15
品牌 Logo 应用领域
日电电子 - NEC 存储内存集成电路静态存储器
页数 文件大小 规格书
28页 367K
描述
Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

UPD4482181GF-A75Y 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:14 X 20 MM, PLASTIC, LQFP-100Reach Compliance Code:compliant
风险等级:5.92Is Samacsys:N
最长访问时间:7.5 ns其他特性:FLOW-THROUGH ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:9437184 bit
内存集成电路类型:CACHE SRAM内存宽度:18
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX18
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.7 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

UPD4482181GF-A75Y 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD4482161, 4482181, 4482321, 4482361  
8M-BIT CMOS SYNCHRONOUS FAST SRAM  
FLOW THROUGH OPERATION  
Description  
The µPD4482161 is a 524,288-word by 16-bit, the µPD4482181 is a 524,288-word by 18-bit, the µPD4482321 is a  
262,144-word by 32-bit and the µPD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with  
advanced CMOS technology using Full-CMOS six-transistor memory cell.  
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 integrate unique synchronous peripheral circuitry, 2-bit  
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single  
clock input (CLK).  
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are suitable for applications which require synchronous  
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In  
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.  
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4  
mm package thickness for high density and low capacitive loading.  
Features  
3.3 V or 2.5 V core supply  
Synchronous operation  
Operating temperature : TA = 0 to 70 °C (-A65, -A75, -A85, -C75, -C85)  
TA = 40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)  
Internally self-timed write control  
Burst read / write : Interleaved burst and linear burst sequence  
Fully registered inputs for flow through operation  
All registers triggered off positive clock edge  
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs  
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)  
Asynchronous output enable : /G  
Burst sequence selectable : MODE  
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482321, µPD4482361)  
/BW1, /BW2, /BWE (µPD4482161, µPD4482181)  
Global write enable : /GW  
Three chip enables for easy depth expansion  
Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M14521EJ3V0DS00 (3rd edition)  
Date Published December 2002 NS CP(K)  
Printed in Japan  
The mark  shows major revised points.  
2000  

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