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UPD44646187F5-E30-FQ1-A PDF预览

UPD44646187F5-E30-FQ1-A

更新时间: 2024-11-09 15:56:07
品牌 Logo 应用领域
日电电子 - NEC 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
36页 397K
描述
DDR SRAM, 4MX18, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

UPD44646187F5-E30-FQ1-A 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:LBGA,Reach Compliance Code:compliant
风险等级:5.78其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e1
长度:17 mm内存密度:75497472 bit
内存集成电路类型:DDR SRAM内存宽度:18
功能数量:1端子数量:165
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX18
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.51 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15 mm
Base Number Matches:1

UPD44646187F5-E30-FQ1-A 数据手册

 浏览型号UPD44646187F5-E30-FQ1-A的Datasheet PDF文件第2页浏览型号UPD44646187F5-E30-FQ1-A的Datasheet PDF文件第3页浏览型号UPD44646187F5-E30-FQ1-A的Datasheet PDF文件第4页浏览型号UPD44646187F5-E30-FQ1-A的Datasheet PDF文件第5页浏览型号UPD44646187F5-E30-FQ1-A的Datasheet PDF文件第6页浏览型号UPD44646187F5-E30-FQ1-A的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
μPD44646095, 44646185, 44646365, 44646097, 44646187, 44646367  
72M-BIT DDR II+ SRAM SEPARATE I/O  
2.0 & 2.5 Cycle Read Latency  
2-WORD BURST OPERATION  
Description  
The μPD44646095 and μPD44646097 are 8,388,608-word by 9-bit, the μPD44646185 and μPD44646187 are  
4,194,304-word by 18-bit and the μPD44646365 and μPD44646367 are 2,097,152-word by 36-bit synchronous double  
data rate static RAMs fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44646xx5 is for 2.0 cycle and the μPD44646xx7 is for 2.5 cycle read latency. The μPD44646095, μPD44646097,  
μPD44646185, μPD44646187, μPD44646365 and μPD44646367 integrate unique synchronous peripheral circuitry and a  
burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage, high density  
and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
Core (VDD) = 1.8 ± 0.1 V power supply  
I/O (VDDQ) = 1.5 ± 0.1 V power supply  
165-pin PLASTIC BGA (15x17)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
DDR read or write operation initiated each cycle  
Pipelined double data rate operation  
Separate data input/output bus  
Two-tick burst for low DDR transaction size  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two Echo clocks (CQ and CQ#)  
Data Valid pin (QVLD) supported  
Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 2,048 cycles after clock is resumed.  
User programmable impedance output (35 to 70 )  
Fast clock cycle time : 2.66 ns (375 MHz) for 2.0 cycle read latency,  
2.5 ns (400 MHz) for 2.5 cycle read latency  
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. M18525EJ1V0DS00 (1st edition)  
Date Published November 2006 NS CP(N)  
Printed in Japan  
2006  

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