Datasheet > UPD44646366F5-E30-FQ1-A

UPD44646366F5-E30-FQ1-A

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
日电电子 - NEC		双倍数据速率静态存储器
页数	文件大小	规格书
36页	401K
描述
DDR SRAM, 2MX36, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

UPD44646366F5-E30-FQ1-A 数据手册

浏览型号UPD44646366F5-E30-FQ1-A的Datasheet PDF文件第2页

浏览型号UPD44646366F5-E30-FQ1-A的Datasheet PDF文件第3页

浏览型号UPD44646366F5-E30-FQ1-A的Datasheet PDF文件第4页

浏览型号UPD44646366F5-E30-FQ1-A的Datasheet PDF文件第5页

浏览型号UPD44646366F5-E30-FQ1-A的Datasheet PDF文件第6页

浏览型号UPD44646366F5-E30-FQ1-A的Datasheet PDF文件第7页

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

72M-BIT DDR II+ SRAM

2.0 & 2.5 Cycle Read Latency

4-WORD BURST OPERATION

Description

The μPD44646094 and μPD44646096 are 8,388,608-word by 9-bit, the μPD44646184 and μPD44646186 are

4,194,304-word by 18-bit and the μPD44646364 and μPD44646366 are 2,097,152-word by 36-bit synchronous double

data rate static RAMs fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44646xx4 is for 2.0 cycle and the μPD44646xx6 is for 2.5 cycle read latency. The μPD44646094, μPD44646096,

μPD44646184, μPD44646186, μPD44646364 and μPD44646366 integrate unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• Core (VDD) = 1.8 ± 0.1 V power supply

I/O (V^DDQ) = 1.5 ± 0.1 V power supply

• 165-pin PLASTIC BGA (15x17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Four - tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two Echo clocks (CQ and CQ#)

• Data Valid pin (QVLD) supported

• Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 2,048 cycles after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 2.66 ns (375 MHz) for 2.0 cycle read latency,

2.5 ns (400 MHz) for 2.5 cycle read latency

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M18524EJ1V0DS00 (1st edition)

Date Published November 2006 NS CP(N)

Printed in Japan

2006

12 3 4 5 6 7...36

下载PDF

与UPD44646366F5-E30-FQ1-A相关器件

型号	品牌	描述	获取价格	数据表
UPD44646366F5-E33-FQ1	NEC	DDR SRAM, 2MX36, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165	获取价格
UPD44646366F5-E33-FQ1-A	NEC	DDR SRAM, 2MX36, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165	获取价格
UPD44646367F5-E25-FQ1-A	NEC	DDR SRAM, 2MX36, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165	获取价格
UPD44647094AF5-E30-FQ1-A	RENESAS	IC,SYNC SRAM,QDR,8MX9,CMOS,BGA,165PIN,PLASTIC	获取价格
UPD44647094AF5-E33-FQ1-A	RENESAS	IC,SYNC SRAM,QDR,8MX9,CMOS,BGA,165PIN,PLASTIC	获取价格
UPD44647094F5-E27-FQ1	NEC	IC,SYNC SRAM,QDR,8MX9,CMOS,BGA,165PIN,PLASTIC	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

UPD44646366F5-E30-FQ1-A

UPD44646366F5-E30-FQ1-A 数据手册

与UPD44646366F5-E30-FQ1-A相关器件

与UPD44646366F5-E30-FQ1-A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

UPD44646366F5-E30-FQ1-A

UPD44646366F5-E30-FQ1-A 数据手册

与UPD44646366F5-E30-FQ1-A相关器件

与UPD44646366F5-E30-FQ1-A相关文章

您还可以找

您在本页遇到什么问题？