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UPD44164184BF5-E50Y-EQ3-A PDF预览

UPD44164184BF5-E50Y-EQ3-A

更新时间: 2024-11-20 20:01:27
品牌 Logo 应用领域
瑞萨 - RENESAS 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
33页 492K
描述
1MX18 DDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165

UPD44164184BF5-E50Y-EQ3-A 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:LBGA,
针数:165Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.84最长访问时间:0.45 ns
其他特性:PIPELINED ARCHITECTUREJESD-30 代码:R-PBGA-B165
长度:15 mm内存密度:18874368 bit
内存集成电路类型:DDR SRAM内存宽度:18
功能数量:1端子数量:165
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX18
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL座面最大高度:1.46 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:13 mm
Base Number Matches:1

UPD44164184BF5-E50Y-EQ3-A 数据手册

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Datasheet  
μPD44164184B  
R10DS0015EJ0200  
Rev.2.00  
18M-BIT DDR II SRAM  
4-WORD BURST OPERATION  
October 6, 2011  
Description  
The μPD44164184B is a 1,048,576-word by 18-bit synchronous double data rate static RAM fabricated with  
advanced CMOS technology using full CMOS six-transistor memory cell.  
The μPD44164184B integrate unique synchronous peripheral circuitry and a burst counter. All input  
registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.  
These products are suitable for application which require synchronous operation, high speed, low voltage,  
high density and wide bit configuration.  
These products are packaged in 165-pin PLASTIC BGA.  
Features  
1.8 0.1 V power supply  
165-pin PLASTIC BGA (13 x 15)  
HSTL interface  
PLL circuitry for wide output data valid window and future frequency scaling  
Pipelined double data rate operation  
Common data input/output bus  
Two-tick burst for low DDR transaction size  
Two input clocks (K and K#) for precise DDR timing at clock rising edges only  
Two output clocks (C and C#) for precise flight time  
and clock skew matching-clock and data delivered together to receiving device  
Internally self-timed write control  
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.  
User programmable impedance output (35 to 70 Ω)  
Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)  
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
R10DS0015EJ0200 Rev.2.00  
October 6, 2011  
Page 1 of 32  

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