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UPD30500AS2-250 PDF预览

UPD30500AS2-250

更新时间: 2024-02-12 12:25:00
品牌 Logo 应用领域
日电电子 - NEC 微控制器和处理器外围集成电路微处理器ISM频段异步传输模式ATM时钟
页数 文件大小 规格书
36页 207K
描述
VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR

UPD30500AS2-250 技术参数

生命周期:Obsolete零件包装代码:BGA
针数:272Reach Compliance Code:unknown
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.83Is Samacsys:N
其他特性:ALSO REQUIRES 3.3V SUPPLY地址总线宽度:64
位大小:64边界扫描:NO
最大时钟频率:100 MHz外部数据总线宽度:64
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-PBGA-B272JESD-609代码:e6
长度:29 mm低功率模式:YES
端子数量:272最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.7 mm
速度:250 MHz最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:MOS
温度等级:OTHER端子面层:TIN BISMUTH
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:10
宽度:29 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

UPD30500AS2-250 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD30500, 30500A, 30500B  
VR5000TM, VR5000ATM, VR5000BTM  
64-BIT MICROPROCESSOR  
DESCRIPTION  
The µPD30500 (VR5000), µPD30500A (VR5000A), and µPD30500BNote (VR5000B) are a high-performance, 64-  
bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by  
MIPSTM Technologies Inc.  
The instructions of the VR5000, VR5000A, and VR5000B are compatible with those of the VR3000TM Series and  
VR4000TM Series and higher, and completely compatible with those of the VR10000TM  
.
Therefore, present  
applications can be used as they are.  
Note Under development  
Detailed functions are described in the following manual. Be sure to read the manual when  
designing your system.  
• VR5000, VR5000A, VR5000B User’s Manual (U11761E)  
FEATURES  
Employs 64-bit MIPS-based RISC architecture  
High-speed processing  
2-way super scalar 5-stage pipeline  
5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (µPD30500)  
6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (µPD30500A)  
8 SPECint95, 8 SPECfp95, 423 MIPS (µPD30500B)  
High-speed translation buffer mechanism (TLB) (48 entries)  
Address space Physical: 36 bits, Virtual: 40 bits  
Floating-point unit (FPU)  
Sum-of-products operation instruction supported  
Primary cache memory (instruction/data: 32 Kbytes each)  
Secondary cache controller  
Maximum operating frequency Internal: 200 MHz (µPD30500), 250 MHz (µPD30500A), 300 MHz (µPD30500B)  
External: 100 MHz  
Selectable external/internal multiple rate from twice to eight times  
Instruction set compatible with VR3000 and VR4000 Series and higher (conforms to MIPS I, II, III, and IV)  
Supply voltage: 3.3 V ±5% (µPD30500)  
Core: 2.5 V ±5%, I/O: 3.3 V ±5% (µPD30500A)  
Core: 1.8 V ±0.1 V, I/O: 3.3 V ±5% (µPD30500B)  
Unless otherwise specified, the VR5000 (µPD30500) is treated as the representative model throughout this  
document.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for availability  
and additional information.  
The mark shows major revised points.  
Document No. U12031EJ4V0DS00 (4th edition)  
Date Published May 2000 N CP(K)  
Printed in Japan  
1997,1999  
©
1997  
MIPS Technologies Inc.  
©

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