Datasheet > UPA2762UGR

UPA2762UGR

更新时间： 2024-10-30 12:16:59

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
8页	207K
描述
MOS FIELD EFFECT TRANSISTOR

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UPA2762UGR 数据手册

Preliminary Data Sheet

μ PA2762UGR

MOS FIELD EFFECT TRANSISTOR

Description

R07DS0011EJ0100

Rev.1.00

Jun 01, 2010

The μ PA2762UGR is N-Channel MOS Field Effect Transistor designed for power management applications of a

notebook computer.

Features

•

Low on-state resistance

⎯ R_DS(on)1= 13.5 mΩ MAX. (V_GS= 10 V, I_D= 12 A)

⎯ R_DS(on)2= 22 mΩ MAX. (V_GS= 4.5 V, I_D= 10 A)

Low Ciss: Ciss = 710 pF TYP. (V_DS= 15 V, V_GS= 0 V)

Small and surface mount package (Power SOP8)

RoHS Compliant

•

Ordering Information

Part No.

LEAD PLATING

PACKING

Package

μ PA2762UGR-E1-AT ^∗

μ PA2762UGR-E2-AT ^∗

Pure Sn (Tin)

Tape 2500 p/reel

Power SOP8

0.08 g TYP.

Note: ^∗1. Pb-free (This product does not contain Pb in external electrode and other parts.)

Absolute Maximum Ratings (T_A= 25°C, All terminals are connected)

Item

Symbol

Ratings

Unit

Drain to Source Voltage (V_GS= 0 V)

Gate to Source Voltage (V_DS= 0 V)

Drain Current (DC)

V_DSS

V_GSS

I_D(DC)

Drain Current (pulse) ^∗

I_D(pulse)

P_T1

Total Power Dissipation ^∗

Total Power Dissipation (PW = 10 sec) ^∗

1.1

°C

P_T2

2.5

Channel Temperature

T_ch

150

Storage Temperature

Single Avalanche Current ^∗

Single Avalanche Energy ^∗

T_stg

I_AS

−55 to +150

E_AS

14.4

Notes: ^∗1. PW ≤ 10 μs, Duty Cycle ≤ 1%

^∗2. Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mmt

^∗3. Starting T_ch= 25°C, V_DD= 17.5 V, R_G= 25 Ω, V_GS= 20 → 0 V, L = 100 μH

R07DS0011EJ0100 Rev.1.00

Jun 01, 2010

Page 1 of 6

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