UL631H256
Low Voltage SoftStore 32K x 8 nvSRAM
Features
Description
F High-performance CMOS non-
The UL631H256 has two separate of a fast SRAM with nonvolatile
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode data integrity.
F 45 and 55 ns Access Times
F 20 and 25 ns Output Enable
Access Times
F Software STORE Initiation
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
and nonvolatile mode. In SRAM Once a STORE cycle is initiated,
mode, the memory operates as an further input or output are disabled
ordinary static RAM. In nonvolatile until the cycle is completed.
operation, data is transferred in Because a sequence of addresses
parallel from SRAM to EEPROM or is used for STORE initiation, it is
from EEPROM to SRAM. In this important that no other read or
mode SRAM functions are disab- write accesses intervene in the
led.
sequence or the sequence will be
F Automatic RECALL on Power Up The UL631H256 is a fast static aborted.
F Software RECALL Initiation
F Unlimited RECALL cycles from
EEPROM
F Unlimited Read and Write to
SRAM
RAM (45 and 55 ns), with a nonvo- Internally, RECALL is a two step
latile electrically erasable PROM procedure. First, the SRAM data is
(EEPROM) element incorporated cleared and second, the nonvola-
in each static memory cell. The tile information is transferred into
SRAM can be read and written an the SRAM cells.
F Wide voltage range: 2.7 ... 3.6 V
F Operating temperature range:
0 to 70 °C
unlimited number of times, while The RECALL operation in no way
independent nonvolatile data resi- alters the data in the EEPROM
des in EEPROM. Data transfers cells. The nonvolatile data can be
-40 to 85 °C
from the SRAM to the EEPROM
recalled an unlimited number of
F CECC 90000 Quality Standard
F ESD protectio > 2000 V
(MIL STD 883C M3015.7-HBM)
F Packages:SOP28 (330 mil)
TSOP32 (Type I)
(the STORE operation), or from the times.
EEPROM to the SRAM (the The UL631H256 is pin compatible
RECALL operation) are initiated with standard SRAMs.
through software sequences.
The UL631H256 combines the
high performance and ease of use
Pin Configuration
Pin Description
G
A11
A9
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
n.c.
A10
E
VCC
W
A13
A8
A9
A11
G
Signal Name Signal Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0 - A14
Address Inputs
Data In/Out
A8
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A13
W
n. c.
VCC
n. c.
A14
DQ0 - DQ7
Chip Enable
E
TSOP
SOP
A10
E
Output Enable
Write Enable
Power Supply Voltage
Ground
G
9
A12 11
DQ7
DQ6
DQ5
DQ4
DQ3
A0
10
11
12
13
14
W
A7
A6
A5
A4
A3
12
13
14
15
16
DQ0
DQ1
DQ2
VSS
VCC
VSS
A1
A2
n.c.
Top View
Top View
1
November 01, 2001