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UL634H256SC35G1 PDF预览

UL634H256SC35G1

更新时间: 2024-11-08 03:23:39
品牌 Logo 应用领域
SIMTEK 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
15页 352K
描述
Low Voltage PowerStore 32K x 8 nvSRAM

UL634H256SC35G1 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP, SOP32,.4Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.7最长访问时间:35 ns
JESD-30 代码:R-PDSO-G32JESD-609代码:e3
长度:20.725 mm内存密度:262144 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3/3.3 V认证状态:Not Qualified
筛选级别:MIL-STD-883座面最大高度:2.54 mm
最大待机电流:0.001 A子类别:SRAMs
最大压摆率:0.045 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.51 mmBase Number Matches:1

UL634H256SC35G1 数据手册

 浏览型号UL634H256SC35G1的Datasheet PDF文件第2页浏览型号UL634H256SC35G1的Datasheet PDF文件第3页浏览型号UL634H256SC35G1的Datasheet PDF文件第4页浏览型号UL634H256SC35G1的Datasheet PDF文件第5页浏览型号UL634H256SC35G1的Datasheet PDF文件第6页浏览型号UL634H256SC35G1的Datasheet PDF文件第7页 
UL634H256  
Low Voltage PowerStore 32K x 8 nvSRAM  
Not Recommended For New Designs  
Features  
Description  
‡
High-performance CMOS non-  
The UL634H256 has two separate The UL634H256 combines the  
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode high performance and ease of use  
‡
‡
35 and 45 ns Access Times  
15 and 20 ns Output Enable  
Access Times  
and nonvolatile mode. In SRAM of a fast SRAM with nonvolatile  
mode, the memory operates as an data integrity.  
ordinary static RAM. In nonvolatile STORE cycles also may be initia-  
operation, data is transferred in ted under user control via a soft-  
parallel from SRAM to EEPROM or ware sequence or via a single pin  
from EEPROM to SRAM. In this (HSB).  
‡
‡
I
CC = 8 mA typ. at 200 ns Cycle  
Time  
Automatic STORE to EEPROM  
on Power Down using external  
capacitor  
mode SRAM functions are disab- Once a STORE cycle is initiated,  
led.  
further input or output are disabled  
‡
‡
‡
‡
Software initiated STORE  
Automatic STORE Timing  
106 STORE cycles to EEPROM  
100 years data retention in  
EEPROM  
The UL634H256 is a fast static until the cycle is completed.  
RAM (35 and 45 ns), with a nonvo- Because a sequence of addresses  
latile electrically erasable PROM is used for STORE initiation, it is  
(EEPROM) element incorporated important that no other read or  
in each static memory cell. The write accesses intervene in the  
‡
‡
‡
Automatic RECALL on Power Up SRAM can be read and written an  
sequence or the sequence will be  
aborted.  
Software RECALL Initiation  
Unlimited RECALL cycles from  
EEPROM  
unlimited number of times, while  
independent nonvolatile data resi-  
des in EEPROM.  
RECALL cycles may also be initia-  
ted by a software sequence.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
cleared and second, the nonvola-  
tile information is transferred into  
the SRAM cells.  
The RECALL operation in no way  
alters the data in the EEPROM  
cells. The nonvolatile data can be  
recalled an unlimited number of  
times.  
‡
‡
Wide voltage range: 2.7 ... 3.6 V  
(3.0 ... 3.6 V for 35 ns type)  
Operating temperature range:  
0 to 70 °C  
Data transfers from the SRAM to  
the EEPROM (the STORE opera-  
tion) take place automatically upon  
power down using charge stored in  
an external 68 μF capacitor. Trans-  
fers from the EEPROM to the  
SRAM (the RECALL operation)  
take place automatically on power  
up.  
-40 to 85 °C  
-40 to 125 °C  
‡
‡
QS 9000 Quality Standard  
ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
RoHS compliance and Pb- free  
Package:SOP32 (300 mil)  
‡
Pin Description  
Pin Configuration  
Signal Name Signal Description  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
VCAP  
A14  
A12  
A7  
VCCX  
HSB  
W
A13  
A8  
A9  
A11  
G
n.c.  
A10  
E
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
2
A0 - A14  
Address Inputs  
Data In/Out  
3
4
DQ0 - DQ7  
5
A6  
6
Chip Enable  
A5  
E
7
A4  
Output Enable  
Write Enable  
8
A3  
G
SOP  
9
n.c.  
A2  
10  
11  
12  
13  
14  
15  
16  
W
A1  
A0  
VCCX  
VSS  
VCAP  
Power Supply Voltage  
Ground  
DQ0  
DQ1  
DQ2  
VSS  
Capacitor  
Top View  
Hardware Controlled Store/Busy  
HSB  
August 15, 2006  
STK Control #ML0058  
1
Rev 1.1  

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