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UCC5681PW28 PDF预览

UCC5681PW28

更新时间： 2024-09-20 15:55:55
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管接口集成电路
页数 文件大小 规格书
7页 111K
描述
9-LINE 105ohm SCSI BUS TERMINATOR, PDSO28, TSSOP-28

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中文翻译

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UCC5681PW28 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：TSSOP, TSSOP28,.25
针数：28Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.92差分输出：YES
接口集成电路类型：SCSI BUS TERMINATORJESD-30 代码：R-PDSO-G28
JESD-609代码：e0长度：9.7 mm
湿度敏感等级：2功能数量：1
信号线数量：9端子数量：28
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP28,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：220
电源：3/5 V标称上拉电阻：105 Ω
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Terminators最大供电电压：5.25 V
最小供电电压：2.7 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

UCC5681PW28 数据手册

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SLUS441A – MARCH 1999 – REVISED AUGUST 2000  
D
LVD-Only Active Termination  
2.7 V to 5.25 V Operation  
Differential Failsafe Bias  
D
D
Standards Supported: SPI-3, Ultra2  
(Fast 40), Ultra3/Ultra160 (Fast 80)  
D
D
D
Reversed Disconnect Polarity  
Built-In SPI-3 Mode Change Filter/Delay  
description  
The UCC5681 is an LVD-only Small Computer System Interface (SCSI) terminator that integrates the mode  
change delay function required by the SPI-3 specification. The device senses what types of SCSI drivers are  
present on the bus via the voltage on the DIFFSENS SCSI control line. Single-ended (SE) and high-voltage  
differential (HVD) SCSI drivers (EIA485) are not supported. If the chip detects the presence of an SE or HVD  
SCSI driver, it disconnects itself by switching all terminating resistors off the bus and enters a high-impedance  
state. The terminator can also be commanded to disconnect the terminating resistors with the DISCNCT input.  
Impedance is trimmed for accuracy and maximum effectiveness. Bus lines are biased to a failsafe state to  
ensure signal integrity.  
The UCC5681 is offered in both 24-pin and 28-pin TSSOP (PW) packages for a temperature range of 0°C to  
70°C.  
functional block diagram  
HIGH–VOLTAGE  
DIFFERENTIAL  
2.15 V  
+
100 ms  
TO  
LOW–VOLTAGE  
DIFFERENTIAL  
DIFFB 11  
300 ms  
DELAY/  
FILTER  
27  
LVD{  
+
0.6 V  
SINGLE–ENDED  
–15 mA≤ I  
≤ –5 mA  
SOURCE  
REF  
1.3V  
12 DIFSENS  
µ
≤
≤
µ
50  
A
I
200 A  
SINK  
124  
56 mV  
REF  
1.25V  
52  
52  
µ
A
10  
–
+
4
3
L1 –  
L1+  
ENABLE  
DISCNCT 15  
TRMPWR 28  
56 mV  
+
–
DIS  
MODE ALL SWITCHES  
124  
56 mV  
SE  
LVD  
HVD  
OPEN  
DOWN  
OPEN  
OPEN  
52  
52  
–
+
DISCNCT  
25 L9 –  
26 L9+  
56 mV  
DISCNCT  
+
–
14  
1
{28-PIN PACKAGE ONLY  
GND  
REG  
UDG–00126  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

中文翻译

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