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SLVS406B – JUNE 2002 – REVISED JUNE 2003
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FEATURES
DESCRIPTION
D
Meets Ultra2 (SPI-2 LVD SCSI), Ultra3, Ultra
160 (SPI-3), Ultra320 (SPI-4), and Ultra640
(SPI-5) Standards
The UCC5696 is a 27-line LVD only SCSI
programmable terminator. The nominal settings
on power up are compliant to SPI-2 through SPI-4.
The programmable settings are used for SPI-5.
The UCC5696 uses the I C to program the
differential impedance and the differential bias
D
D
D
D
2.7-V to 5.25-V Termpwr Operation
Differential Fail-Safe Bias
2
2
I C Bus Adjustable Impedance and
current.
The
differential
impedance
is
Differential Bias Current
programmed in 5-Ω increments from 55 Ω to
130 Ω using 4 bits (16 steps). The differential bias
current is programmed in 50 µA from 0.7 mA to
1.45 mA using 4 bits (16 steps). The UCC5696
has the SPI-3 mode change delay, the typical
value is 200 ms.
80-Pin Low Profile Quad Flat Pack Package
(QFP)
APPLICATION DIAGRAM
UCC5696
PVDD
UCC5696
L1+
L1–
1
2
1
2
L1+
L1–
8
PVDD
8
7
Termpower
Termpower
7
TERMPWR
TERMPWR
CONTROL LINES (9)
4.7µF
4.7 F
µ
L9+ 30
L9– 29
30 L9+
29 L9–
DIFSENS 15
15 DIFSENS
50 ICBD
51 ICBC
ICBD 50
ICBC 51
2
2
CBUS
I
CBUS
I
Ω
20 k
Ω
20 k
DIFFB 16
16 DIFFB
µ
F
µ
F
0.1
0.1
49 ICAD0
43 ICAD6
ICAD0 49
ICAD6 43
L10+ 32
L10– 31
32 L10+
31 L10–
2
2
I
C Address
I
C Address
DATA (9)
LOW BYTE 0–7
+ PARITY LINES
L18+ 61
L18– 62
61 L18+
62 L18–
DISCNCT
52
DISCNCT 52
L19+ 63
L19– 64
63 L19+
64 L19–
DATA (9)
HIGH BYTE 8–15
+ PARITY LINES
10
10
REG
REG
µ
4.7
F
L27+ 79
79 L27+
80 L27–
4.7
µ
F
L27– 80
GND
GND
54
54
UDG–01093
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002, Texas Instruments Incorporated
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