Datasheet > TSI205-A

TSI205-A

更新时间： 2024-09-20 15:55:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
26页	207K
描述
Power Management Circuit

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技术参数
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TSI205-A 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.84
Base Number Matches：	1

TSI205-A 数据手册

Datasheet

Tsi205 Primary Side Monitor

Features

Description

The Tsi205 is designed to monitor parameters on

the high voltage primary side of an on-card power

system in a distributed power architecture.

•

Input voltage measurement (24 V or 48 V)

10-bit analog-to-digital converter (ADC)

Input voltage measurement accuracy 0.5%

Fuse status monitoring, high and low side

Primary current sensing and measurement

Primary side undervoltage, overvoltage and

brownout detection

In a typical 24 V or 48 V application, the Tsi205

measures input voltage and current and transmits

the digitized values through a serial interface to the

secondary side controller (Tsi257). Input

overvoltage (OV) and undervoltage (UV) detection

are provided, with programmable thresholds set by

external resistors.

•

Input UV shutdown accuracy <1%

Isolated PI-Link interface to secondary side

controller transmits primary voltage, current,

fuse status and input status data

•

Compatible with standard inrush limiters

Self-powered from 24 V or 48 V nominal

The Tsi205 provides on-off control for an isolated

power converter that supplies the intermediate bus

voltage for the card. The Tsi205 monitors the status

of up to four input fuses, both high side and low

side. Fuse status information is transmitted to the

secondary side through the serial PI-Link interface.

Applications

•

Telecom and datacom cards

ATCA (Advanced Telecom Compute

Architecture) systems

•

Industrial controllers

Single board computers

Figure 1 — Typical application circuit

0 V

(Battery

return)

EMI

filter

Intermediate

bus (IB) brick

C_IN

Enable

IB rail

Power connections

shown as

R1 R2

R17

OP1

Tsi205

VDD

VDDO

ENABLE

TX_H

R16

Seat

SHUNT

SEAT

(short pins)

TX_L

Brick

shutdown

signal

from

Tsi257

BUSOFF

FETA

OP2

R13

VBATT

FUSE_H

FUSE_L

VBG

SENSE_P

SENSE_OUT

SENSE_IN

R15

R12

R19

PI-Link

interface

to Tsi257

R14

SENSE_N

POR

VSS

Isolation

circuit

(see Fig. 7)

VSSO

AUX

BIAS

R10

-48 V A

Primary

Secondary

Fuse A

R11

Inrush

limit

R18

Fuse B

controller

-48 V B

MD502J

Note: High-side fuse monitoring is not shown – refer to Figure 8.

80C6000_MA001_01 April 2006

- 1 -

12 3 4 5 6 7...26

中文翻译

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