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TPS1100PWLE PDF预览

TPS1100PWLE

更新时间: 2024-11-23 12:05:55
品牌 Logo 应用领域
德州仪器 - TI 晶体小信号场效应晶体管开关光电二极管
页数 文件大小 规格书
14页 700K
描述
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

TPS1100PWLE 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-8针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8541.21.00.95风险等级:5.17
Is Samacsys:N其他特性:LOGIC LEVEL COMPATIBLE, ESD PROTECTED
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:15 V
最大漏极电流 (Abs) (ID):1.27 A最大漏极电流 (ID):1.27 A
最大漏源导通电阻:0.4 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PDSO-G8元件数量:1
端子数量:8工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:P-CHANNEL
最大功率耗散 (Abs):0.504 W认证状态:Not Qualified
子类别:Other Transistors表面贴装:YES
端子形式:GULL WING端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

TPS1100PWLE 数据手册

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TPS1100, TPS1100Y  
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS  
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995  
D OR PW PACKAGE  
Low r  
. . . 0.18 Typ at V  
= 10 V  
DS(on)  
GS  
(TOP VIEW)  
3 V Compatible  
Requires No External V  
SOURCE  
SOURCE  
SOURCE  
GATE  
DRAIN  
DRAIN  
DRAIN  
DRAIN  
1
2
3
4
8
7
6
5
CC  
TTL and CMOS Compatible Inputs  
= 1.5 V Max  
V
GS(th)  
Available in Ultrathin TSSOP Package (PW)  
ESD Protection Up to 2 kV Per  
MIL-STD-883C, Method 3015  
D PACKAGE  
PW PACKAGE  
description  
The TPS1100 is  
a
single P-channel  
enhancement-mode MOSFET. The device has  
been optimized for 3-V or 5-V power distribution  
in battery-powered systems by means of Texas  
Instruments LinBiCMOS  
process. With  
a
schematic  
maximum V of 1.5 V and an I  
of only  
GS(th)  
DSS  
SOURCE  
0.5 µA, the TPS1100 is the ideal high-side switch  
for low-voltage, portable battery-management  
systemswheremaximizingbatterylifeisaprimary  
concern. The low r  
and excellent ac  
DS(on)  
ESD-  
characteristics (rise time 10 ns typical) make the  
TPS1100 the logical choice for low-voltage  
switching applications such as power switches for  
pulse-width-modulated (PWM) controllers or  
motor/bridge drivers.  
Protection  
Circuitry  
GATE  
The ultrathin thin shrink small-outline package or  
TSSOP (PW) version with its smaller footprint and  
reduction in height fits in places where other  
P-channel MOSFETs cannot. The size advantage  
is especially important where board real estate is  
at a premium and height restrictions do not allow  
for a small-outline integrated circuit (SOIC)  
package.  
DRAIN  
NOTE A: For all applications, all source pins should be connected  
and all drain pins should be connected.  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
SMALL OUTLINE PLASTIC DIP  
CHIP FORM  
(Y)  
T
A
(D)  
(P)  
40°C to 85°C  
TPS1100D  
TPS1100PWLE  
TPS1100Y  
The D package is available taped and reeled. Add an R suffix to device type (e.g.,  
TPS1100DR). The PW package is available only left-end taped and reeled  
(indicated by the LE suffix on the device type; e.g., TPS1100PWLE). The chip form  
is tested at 25°C.  
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic  
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to  
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than  
maximum-rated voltages to these high-impedance circuits.  
LinBiCMOS is a trademark of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

TPS1100PWLE 替代型号

型号 品牌 替代类型 描述 数据表
TPS1100PWG4 TI

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