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TPS1110 PDF预览

TPS1110

更新时间: 2024-11-19 12:22:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
14页 242K
描述
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS

TPS1110 数据手册

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TPS1110, TPS1110Y  
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS  
SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998  
D PACKAGE  
(TOP VIEW)  
Low r  
. . . 65 mTyp at V  
= 4.5 V  
DS(on)  
GS  
High Current Capability  
6 A at V = 4.5 V  
GS  
SOURCE  
SOURCE  
SOURCE  
GATE  
DRAIN  
DRAIN  
DRAIN  
DRAIN  
1
2
3
4
8
7
6
5
Logic-Level Gate Drive (3 V Compatible)  
= 0.9 V Max  
V
GS(th)  
Low Drain-Source Leakage Current  
<100 nA From 25°C to 75°C  
at V  
= 6 V  
DS  
Fast Switching . . . 5.8 ns Typ t  
d(on)  
Small-Outline Surface-Mount Power  
Package  
description  
The TPS1110 is a single, low-r  
, P-channel enhancement-mode power MOS transistor. The device  
DS(on)  
features extremely low-r  
values coupled with logic-level gate-drive capability and very low drain-source  
DS(on)  
leakage current. With a maximum V  
of 0.9 V and an I  
of only –100 nA, the TPS1110 is the ideal  
GS(th)  
DSS  
high-side switch for low-voltage, portable battery-management power-distribution systems where maximizing  
battery life is an important concern. The thermal performance of the 8-pin small-outline (D) package has been  
greatly enhanced over the standard 8-pin SOIC, further making the TPS1110 ideally suited for many power  
applications. For compatibility with existing designs, the TPS1110 has a pinout common with other P-channel  
MOSFETs in small-outline integrated circuit (SOIC) packages. The TPS1110 is characterized for an operating  
junction temperature range, T , from 40°C to 150°C. TheDpackageisavailablepackagedinstandardsleeves  
J
or in taped and reeled formats. When ordering the tape-and-reel format, add an R suffix to the device type  
number (e.g., TPS1110DR).  
AVAILABLE OPTIONS  
PACKAGED DEVICE  
CHIP FORM  
(Y)  
T
J
SMALL OUTLINE  
(D)  
40°C to 150°C  
TPS1110D  
TPS1110Y  
The D package is available taped and reeled. Add an R suffix to device  
type (e.g., TPS1110DR). The chip form is tested at 25°C.  
schematic  
SOURCE  
1
2
3
4
GATE  
5
6
7
8
DRAIN  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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