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TN0604N3 PDF预览

TN0604N3

更新时间： 2024-11-11 22:42:07
品牌 Logo 应用领域
超科 - SUPERTEX 晶体小信号场效应晶体管开关输入元件
页数 文件大小 规格书
4页 45K
描述
N-Channel Enhancement-Mode Vertical DMOS FETs

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中文翻译

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TN0604N3 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：CYLINDRICAL, O-PBCY-W3Reach Compliance Code：compliant
ECCN代码：EAR99风险等级：5.26
Is Samacsys：N其他特性：LOGIC LEVEL COMPATIBLE, HIGH INPUT IMPEDANCE
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：40 V
最大漏极电流 (Abs) (ID)：1 A最大漏极电流 (ID)：0.7 A
最大漏源导通电阻：1.6 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：50 pFJEDEC-95代码：TO-92
JESD-30 代码：O-PBCY-W3JESD-609代码：e0
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：PLASTIC/EPOXY封装形状：ROUND
封装形式：CYLINDRICAL峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL最大功率耗散 (Abs)：1 W
认证状态：Not Qualified子类别：FET General Purpose Power
表面贴装：NO端子面层：Tin/Lead (Sn/Pb)
端子形式：WIRE端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

TN0604N3 数据手册

 浏览型号TN0604N3的Datasheet PDF文件第2页浏览型号TN0604N3的Datasheet PDF文件第3页浏览型号TN0604N3的Datasheet PDF文件第4页 
TN0604  
Low Threshold  
N-Channel Enhancement-Mode  
Vertical DMOS FETs  
Ordering Information  
Order Number / Package  
BVDSS  
/
RDS(ON)  
(max)  
ID(ON)  
(min)  
VGS(th)  
(max)  
BVDGS  
40V  
TO-92  
TN0604N3  
—
SOW-20*  
—
0.75Ω  
1.0Ω  
4.0A  
4.0A  
1.6V  
1.6V  
40V  
TN0604WG  
* Same as SO-20 with 300 mil wide body.  
Features  
❏ Low threshold — 1.6V max.  
Low Threshold DMOS Technology  
These low threshold enhancement-mode (normally-off) transis-  
tors utilize a vertical DMOS structure and Supertex's well-proven  
silicon-gate manufacturing process. This combination produces  
devices with the power handling capabilities of bipolar transistors  
and with the high input impedance and positive temperature  
coefficient inherent in MOS devices. Characteristic of all MOS  
structures, these devices are free from thermal runaway and  
thermally-induced secondary breakdown.  
❏ High input impedance  
❏ Low input capacitance — 140pF typical  
❏ Fast switching speeds  
❏ Low on resistance  
❏ Free from secondary breakdown  
❏ Low input and output leakage  
❏ Complementary N- and P-channel devices  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where very low threshold  
voltage, highbreakdownvoltage, highinputimpedance, lowinput  
capacitance, and fast switching speeds are desired.  
Applications  
❏ Logic level interfaces – ideal for TTL and CMOS  
Package Options  
❏ Solid state relays  
❏ Battery operated systems  
❏ Photo voltaic drives  
❏ Analog switches  
❏ General purpose line drivers  
❏ Telecom switches  
Absolute Maximum Ratings  
Drain-to-Source Voltage  
Drain-to-Gate Voltage  
Gate-to-Source Voltage  
S G D  
BVDSS  
BVDGS  
± 20V  
SOW-20  
TO-92  
Operating and Storage Temperature  
Soldering Temperature*  
-55°C to +150°C  
300°C  
Notes:  
1. See Package Outline section for dimensions.  
2. See Array section for quad pinouts.  
*
Distance of 1.6 mm from case for 10 seconds.  
02/06/02  
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability  
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to  
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the  
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.  
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