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TN0604N3-GP014

更新时间： 2024-11-13 01:02:15
品牌 Logo 应用领域
超科 - SUPERTEX 输入元件开关晶体管
页数 文件大小 规格书
5页 647K
描述
N-Channel Enhancement-Mode Vertical DMOS FET

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中文翻译

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TN0604N3-GP014 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：CYLINDRICAL, O-PBCY-T3Reach Compliance Code：unknown
风险等级：5.65配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：40 V最大漏极电流 (ID)：0.7 A
最大漏源导通电阻：0.75 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：50 pFJEDEC-95代码：TO-92
JESD-30 代码：O-PBCY-T3JESD-609代码：e3
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装形状：ROUND封装形式：CYLINDRICAL
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
功耗环境最大值：0.74 W表面贴装：NO
端子面层：Matte Tin (Sn)端子形式：THROUGH-HOLE
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

TN0604N3-GP014 数据手册

 浏览型号TN0604N3-GP014的Datasheet PDF文件第2页浏览型号TN0604N3-GP014的Datasheet PDF文件第3页浏览型号TN0604N3-GP014的Datasheet PDF文件第4页浏览型号TN0604N3-GP014的Datasheet PDF文件第5页 
Supertex inc.  
TN0604  
N-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
► Low threshold (1.6V max.)  
► High input impedance  
► Low input capacitance (140pF typical)  
► Fast switching speeds  
► Low on-resistance  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structure and Supertex’s  
well-proven, silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and the high input impedance  
and positive temperature coefficient inherent in MOS devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced secondary  
breakdown.  
► Free from secondary breakdown  
► Low input and output leakage  
Applications  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
► Logic level interfaces - ideal for TTL and CMOS  
► Solid state relays  
► Battery operated systems  
► Photo voltaic drives  
► Analog switches  
► General purpose line drivers  
► Telecom switches  
Ordering Information  
Product Summary  
RDS(ON)  
ID(ON)  
Part Number  
Package Option  
Packing  
VGS(th)  
(max)  
BVDSS/BVDGS  
(max)  
(min)  
TN0604N3-G  
TO-92  
1000/Bag  
40V  
0.75Ω  
4.0A  
1.6V  
TN0604N3-G P002  
TN0604N3-G P003  
Pin Configuration  
TN0604N3-G P005 TO-92  
TN0604N3-G P013  
2000/Reel  
TN0604N3-G P014  
DRAIN  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
SOURCE  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
GATE  
TO-92  
Absolute Maximum Ratings  
Parameter  
Value  
BVDSS  
BVDGS  
±20V  
Product Marking  
Drain-to-source voltage  
Drain-to-gate voltage  
SiTN  
0 6 0 4  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
= “Green” Packaging  
Gate-to-source voltage  
Operating and storage temperature  
-55OC to +150OC  
Package may or may not include the following marks: Si or  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
TO-92  
Typical Thermal Resistance  
Package  
θja  
TO-92  
132OC/W  
Doc.# DSFP-TN0604  
D080813  
Supertex inc.  
www.supertex.com  
12345

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