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TN0604WG-G

更新时间： 2024-11-12 03:02:31
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
6页 728K
描述
N-Channel Enhancement-Mode Vertical DMOS FET

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中文翻译

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TN0604WG-G 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SMALL OUTLINE, R-PDSO-G20
针数：20Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8541.29.00.75
风险等级：5.66其他特性：LOW THRESHOLD, LOGIC LEVEL COMPATIBLE
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：40 V
最大漏极电流 (ID)：1 A最大漏源导通电阻：1 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJEDEC-95代码：MS-013AC
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
湿度敏感等级：1元件数量：1
端子数量：20工作模式：ENHANCEMENT MODE
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL最大脉冲漏极电流 (IDM)：4 A
认证状态：Not Qualified表面贴装：YES
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

TN0604WG-G 数据手册

 浏览型号TN0604WG-G的Datasheet PDF文件第2页浏览型号TN0604WG-G的Datasheet PDF文件第3页浏览型号TN0604WG-G的Datasheet PDF文件第4页浏览型号TN0604WG-G的Datasheet PDF文件第5页浏览型号TN0604WG-G的Datasheet PDF文件第6页 
TN0604  
N-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
► Low threshold — 1.6V max.  
► High input impedance  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structure and Supertex’s  
well-proven, silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and the high input  
impedance and positive temperature coefficient inherent  
in MOS devices. Characteristic of all MOS structures, this  
device is free from thermal runaway and thermally-induced  
secondary breakdown.  
► Low input capacitance — 140pF typical  
► Fast switching speeds  
► Low on-resistance  
► Free from secondary breakdown  
► Low input and output leakage  
► Complementary N- and P-channel devices  
Supertex’s vertical DMOS FETs are ideally suited to a  
wide range of switching and amplifying applications where  
very low threshold voltage, high breakdown voltage, high  
input impedance, low input capacitance, and fast switching  
speeds are desired.  
Applications  
► Logic level interfaces – ideal for TTL and CMOS  
► Solid state relays  
► Battery operated systems  
► Photo voltaic drives  
► Analog switches  
► General purpose line drivers  
► Telecom switches  
The Quad-Array package (20-Lead SOW (WG)) uses  
four independent DMOS transistors which provide four  
independent channels.  
Ordering Information  
RDS(ON)  
ID(ON)  
min  
(A)  
VGS(th)  
max  
(V)  
Package Options  
BVDSS/BVDGS  
max  
(V)  
TO-92  
20-Lead SOW  
(Ω)  
40  
40  
0.75  
1.0  
4.0  
4.0  
1.6  
1.6  
TN0604N3-G  
-
-
TN0604WG-G  
-G indicates package is RoHS compliant (‘Green’)  
DRAIN4  
Pin Configurations  
Absolute Maximum Ratings  
Parameter  
Drain-to-source voltage  
Drain-to-gate voltage  
Gate-to-source voltage  
Operating and storage temperature -55OC to +150OC  
DRAIN4  
DRAIN4  
GATE4  
Value  
BVDSS  
BVDGS  
20V  
SOURCE4  
SOURCE3  
GATE3  
DRAIN1  
DRAIN1  
DRAIN1  
DRAIN3  
DRAIN3  
SOURCE  
GATE  
DRAIN3  
GATE1  
SOURCE1  
SOURCE2  
DRAIN  
GATE2  
DRAIN2  
DRAIN2  
DRAIN2  
Soldering temperature*  
300OC  
TO-92 (N3)  
20-Lead SOW (WG)  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
Product Marking  
Top Marking  
* Distance of 1.6mm from case for 10 seconds.  
YY = Year Sealed  
YYWW  
TN0604WG  
WW = Week Sealed  
LLLLLLLLLL  
L = Lot Number  
Product Marking  
C = Country of Origin*  
A = Assembler ID*  
Bottom Marking  
TN  
YY = Year Sealed  
0604  
= “Green” Packaging  
WW = Week Sealed  
CCCCCCCCCCC  
AAA  
YYWW  
*May be part of top marking  
= “Green” Packaging  
TO-92 (N3)  
20-Lead SOW (WG)  
123456

中文翻译

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