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TN0604N3-GP013 PDF预览

TN0604N3-GP013

更新时间: 2024-11-13 01:02:15
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
5页 647K
描述
N-Channel Enhancement-Mode Vertical DMOS FET

TN0604N3-GP013 数据手册

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Supertex inc.  
TN0604  
N-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
Low threshold (1.6V max.)  
High input impedance  
Low input capacitance (140pF typical)  
Fast switching speeds  
Low on-resistance  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structure and Supertex’s  
well-proven, silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and the high input impedance  
and positive temperature coefficient inherent in MOS devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced secondary  
breakdown.  
Free from secondary breakdown  
Low input and output leakage  
Applications  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
Logic level interfaces - ideal for TTL and CMOS  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
General purpose line drivers  
Telecom switches  
Ordering Information  
Product Summary  
RDS(ON)  
ID(ON)  
Part Number  
Package Option  
Packing  
VGS(th)  
(max)  
BVDSS/BVDGS  
(max)  
(min)  
TN0604N3-G  
TO-92  
1000/Bag  
40V  
0.75Ω  
4.0A  
1.6V  
TN0604N3-G P002  
TN0604N3-G P003  
Pin Configuration  
TN0604N3-G P005 TO-92  
TN0604N3-G P013  
2000/Reel  
TN0604N3-G P014  
DRAIN  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
SOURCE  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
GATE  
TO-92  
Absolute Maximum Ratings  
Parameter  
Value  
BVDSS  
BVDGS  
±20V  
Product Marking  
Drain-to-source voltage  
Drain-to-gate voltage  
SiTN  
0 6 0 4  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
= “Green” Packaging  
Gate-to-source voltage  
Operating and storage temperature  
-55OC to +150OC  
Package may or may not include the following marks: Si or  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
TO-92  
Typical Thermal Resistance  
Package  
θja  
TO-92  
132OC/W  
Doc.# DSFP-TN0604  
D080813  
Supertex inc.  
www.supertex.com  

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