TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
Organization . . . 1M × 8 × 2 Banks
DGE PACKAGE
( TOP VIEW )
3.3-V Power Supply (±10% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
V
SS
DQ7
CC
2
DQ0
High Bandwidth – Up to 83-MHz Data Rates
3
V
V
SSQ
DQ6
SSQ
DQ1
CAS Latency Programmable to 2 or 3
Cycles From Column-Address Entry
4
5
V
V
CCQ
DQ5
CCQ
DQ2
Burst Sequence Programmable to Serial or
Interleave
6
7
V
V
SSQ
DQ4
SSQ
DQ3
Burst Length Programmable to 1, 2, 4, or 8
8
Chip Select and Clock Enable for
Enhanced-System Interfacing
9
V
V
CCQ
CCQ
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
DQM
CLK
CKE
NC
A9
Cycle-by-Cycle DQ-Bus Mask Capability
Auto-Refresh and Self-Refresh Capability
4K Refresh (Total for Both Banks)
NC
W
CAS
RAS
CS
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
A11
A10
A0
A8
Compatible With JEDEC Standards
Pipeline Architecture
A7
A1
A6
Temperature Ranges
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
A2
A5
A3
A4
V
V
SS
CC
Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
REFRESH
INTERVAL
PIN NOMENCLATURE
A0–A10 Address Inputs
t
t
t
t
CK2
CK3
CK2
CK3
(CL = 3) (CL = 2) (CL = 3) (CL = 2)
A0–A10 Row Addresses
A0–A8 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
†
’626812-12A
12 ns
12 ns
15 ns
18 ns
9 ns
9 ns
9 ns
64 ms
64 ms
’626812-12
10 ns
†
A11
CAS
CKE
CLK
CS
–12A speed device is supported only at –5/+10% V
CC
description
System Clock
Chip Select
The TMS626812 is a high-speed 16777216-bit
synchronous dynamic random access memory
(SDRAM) device organized as two banks of
1048576 words with eight bits per word.
DQ0–DQ7
SDRAM Data Input/Output
Data/Output Mask Enable
No External Connect
DQM
NC
RAS
Row-Address Strobe
Power Supply (3.3-V Typ)
Power Supply for Output Drivers (3.3-V Typ)
Ground
Ground for Output Drivers
Write Enable
V
V
V
V
CC
CCQ
SS
SSQ
All inputs and outputs of the TMS626812 series
are compatible with the LVTTL interface.
W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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