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TMS664164-12DGE PDF预览

TMS664164-12DGE

更新时间: 2024-10-28 15:54:51
品牌 Logo 应用领域
德州仪器 - TI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
56页 929K
描述
4MX16 CACHE DRAM, 8ns, PDSO54

TMS664164-12DGE 技术参数

生命周期:Obsolete包装说明:TSOP2,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:8 ns
JESD-30 代码:R-PDSO-G54长度:22.22 mm
内存密度:67108864 bit内存集成电路类型:CACHE DRAM
内存宽度:16功能数量:1
端口数量:2端子数量:54
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

TMS664164-12DGE 数据手册

 浏览型号TMS664164-12DGE的Datasheet PDF文件第2页浏览型号TMS664164-12DGE的Datasheet PDF文件第3页浏览型号TMS664164-12DGE的Datasheet PDF文件第4页浏览型号TMS664164-12DGE的Datasheet PDF文件第5页浏览型号TMS664164-12DGE的Datasheet PDF文件第6页浏览型号TMS664164-12DGE的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃ ꢃ ꢄ ꢄ ꢅꢄ ꢆ ꢀ ꢁꢂ ꢃ ꢃ ꢄ ꢇꢅ ꢄ ꢆ ꢀ ꢁ ꢂꢃ ꢃꢄ ꢅꢃ ꢄ  
ꢄ ꢅ ꢈ ꢄ ꢉ ꢊ ꢄ ꢋꢌ ꢄ ꢍꢋꢎ ꢀꢏ ꢐ ꢊ ꢈ ꢑ ꢅ ꢒ ꢐ ꢋꢌ ꢇ ꢍꢋꢎ ꢀꢏ ꢅ ꢊ ꢄ ꢇ ꢒ ꢑ ꢃ ꢋꢌ ꢅ ꢃ ꢍꢋꢎ ꢀ ꢋ ꢌ ꢄꢍ ꢋ ꢓꢔ ꢕ  
SMOS695A − APRIL 1998 − REVISED JULY 1998  
D
Organization . . .  
D
D
D
D
Pipeline Architecture (Single-Cycle  
Architecture)  
1048576 x 16 Bits x 4 Banks  
2097152 x 8 Bits x 4 Banks  
4194304 x 4 Bits x 4 Banks  
Single Write/Read Burst  
Self-Refresh Capability (Every 16 ms)  
D
D
3.3-V Power Supply ( 10% Tolerance)  
Low-Noise, Low-Voltage  
Transistor-Transistor Logic (LVTTL)  
Interface  
Four Banks for On-Chip Interleaving for  
x8/x16 (Gapless Access) Depending on  
Organizations  
D
D
D
D
D
Power-Down Mode  
D
High Bandwidth − Up to 125-MHz Data  
Rates  
Compatible With JEDEC Standards  
16K RAS-Only Refresh (Total for All Banks)  
4K Auto Refresh (Total for All Banks)/64 ms  
D
Burst Length Programmable to 1, 2, 4, 8  
D
Programmable Output Sequence − Serial or  
Interleave  
Automatic Precharge and Controlled  
Precharge  
D
Chip-Select and Clock-Enable for  
Enhanced-System Interfacing  
D
Burst Interruptions Supported:  
− Read Interruption  
− Write Interruption  
D
Cycle-by-Cycle DQ Bus Mask Capability  
D
Only x16 SDRAM Configuration Supports  
Upper-/Lower-Byte Masking Control  
− Precharge Interruption  
D
D
Support Clock-Suspend Operation (Hold  
Command)  
D
D
Programmable CAS Latency From Column  
Address  
Intel PC100 Compliant (-8 and -8A parts)  
Performance Ranges:  
SYNCHRONOUS  
CLOCK CYLE  
TIME  
ACCESS TIME  
CLOCK TO  
OUTPUT  
REFRESH  
INTERVAL  
t
t
t
t
t
REF  
CK3  
CK2  
AC3  
AC2  
’664xx4-8  
’664xx4-8A  
’664xx4-10  
8 ns  
8 ns  
10 ns  
15 ns  
15 ns  
6 ns  
6 ns  
6 ns  
64 ms  
64 ms  
64 ms  
7.5 ns  
7.5 ns  
10 ns  
7.5 ns  
description  
The TMS664xx4 series are 67108864-bit synchronous dynamic random-access memory (SDRAM) devices  
which are organized as follow:  
D
D
D
Four banks of 1 048 576 words with 16 bits per word  
Four banks of 2097152 words with 8 bits per word  
Four banks of 4194304 words with 4 bits per word  
All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface.  
The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and  
outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed  
microprocessors and caches.  
The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP)  
(DGE suffix).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢩ  
Copyright 1998, Texas Instruments Incorporated  
ꢥ ꢩ ꢦ ꢥꢞ ꢟꢳ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢮ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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SDRAM|4X1MX16|CMOS|TSOP|54PIN|PLASTIC
TMS664414 TI

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4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
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4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA