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TMS664414-8ADGE

更新时间： 2024-10-28 15:54:51
品牌 Logo 应用领域
德州仪器 - TI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
56页 957K
描述
16MX4 SYNCHRONOUS DRAM, 6ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54

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TMS664414-8ADGE 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：54
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.32
访问模式：FOUR BANK PAGE BURST最长访问时间：6 ns
其他特性：RAS ONLY/AUTO/SELF REFRESHJESD-30 代码：R-PDSO-G54
长度：22.22 mm内存密度：67108864 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：4
功能数量：1端口数量：1
端子数量：54字数：16777216 words
字数代码：16000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：16MX4封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE认证状态：Not Qualified
座面最大高度：1.2 mm自我刷新：YES
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL宽度：10.16 mm
Base Number Matches：1

TMS664414-8ADGE 数据手册

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TMS664414, TMS664814, TMS664164  
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK  
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES  
SMOS695A – APRIL 1998 – REVISED JULY 1998  
Organization . . .  
Pipeline Architecture (Single-Cycle  
1048576 x 16 Bits x 4 Banks  
2097152 x 8 Bits x 4 Banks  
4194304 x 4 Bits x 4 Banks  
Architecture)  
Single Write/Read Burst  
Self-Refresh Capability (Every 16 s)  
3.3-V Power Supply (±10% Tolerance)  
Low-Noise, Low-Voltage  
Transistor-Transistor Logic (LVTTL)  
Interface  
Four Banks for On-Chip Interleaving for  
x8/x16 (Gapless Access) Depending on  
Organizations  
Power-Down Mode  
High Bandwidth – Up to 125-MHz Data  
Rates  
Compatible With JEDEC Standards  
16K RAS-Only Refresh (Total for All Banks)  
4K Auto Refresh (Total for All Banks)/64 ms  
Burst Length Programmable to 1, 2, 4, 8  
Programmable Output Sequence – Serial or  
Interleave  
Automatic Precharge and Controlled  
Precharge  
Chip-Select and Clock-Enable for  
Enhanced-System Interfacing  
Burst Interruptions Supported:  
– Read Interruption  
– Write Interruption  
Cycle-by-Cycle DQ Bus Mask Capability  
Only x16 SDRAM Configuration Supports  
Upper-/Lower-Byte Masking Control  
– Precharge Interruption  
Support Clock-Suspend Operation (Hold  
Command)  
Programmable CAS Latency From Column  
Address  
Intel PC100 Compliant (-8 and -8A parts)  
Performance Ranges:  
SYNCHRONOUS  
CLOCK CYLE  
TIME  
ACCESS TIME  
CLOCK TO  
OUTPUT  
REFRESH  
INTERVAL  
t
t
t
t
t
REF  
CK3  
CK2  
AC3  
AC2  
’664xx4-8  
’664xx4-8A  
’664xx4-10  
8 ns  
8 ns  
10 ns  
15 ns  
15 ns  
6 ns  
6 ns  
6 ns  
64 ms  
64 ms  
64 ms  
7.5 ns  
7.5 ns  
10 ns  
7.5 ns  
description  
The TMS664xx4 series are 67108864-bit synchronous dynamic random-access memory (SDRAM) devices  
which are organized as follow:  
Four banks of 1 048 576 words with 16 bits per word  
Four banks of 2097152 words with 8 bits per word  
Four banks of 4194304 words with 4 bits per word  
All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface.  
The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and  
outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed  
microprocessors and caches.  
The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP)  
(DGE suffix).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...56

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与TMS664414-8ADGE相关器件

型号 品牌 获取价格 描述 数据表
TMS664414DGE-10 TI

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 		16MX4 SYNCHRONOUS DRAM, 7.5ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
TMS664414DGE-8 TI

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 		16MX4 SYNCHRONOUS DRAM, 6ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
TMS664414DGE-8A TI

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 		16MX4 SYNCHRONOUS DRAM, 6ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
TMS664814 TI

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 		4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
TMS66481410 TI

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 		4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
TMS6648148 TI

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 		4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
TMS6648148A TI

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 		4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RA
TMS664814-8ADGE TI

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 		8MX8 SYNCHRONOUS DRAM, 6ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
TMS664814-8DGE TI

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 		8MX8 SYNCHRONOUS DRAM, 6ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
TMS664814DGE-10 TI

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 		8MX8 SYNCHRONOUS DRAM, 7.5ns, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54

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